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Graphics Databook

Second Edition 1990
INMOS document number: 72-TRN-204-01
268 Pages

© INMOS Limited 1990. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.

Preface

frontcover 72-TRN-204-01

Graphics processing is a significant area of application for INMOS devices. The INMOS Graphics Databook has been published to provide comprehensive information regarding the current range of INMOS graphics devices.

The databook comprises an INMOS overview, engineering data and applications Information for the INMOS IMS G171, G176 and G178 Colour Look-Up Tables (CLUTs), the INMOS IMS G300, G332 and G364 Colour Video Controllers (CVC) and the INMOS G180 high performance CLUT.

The INMOS family of colour look-up tables provide the analogue output stages for colour graphic systems. The device consists of a high-speed random access store or look-up table, three DACs, a pixel word mask and a microprocessor interface.

The INMOS family of colour video controllers provide all necessary functions for controlling real time operation of a raster scan video system, using dual ported DRAMs. The devices integrate all video timing and control circuitry, bit map to screen refresh management, colour expansion and gamma correction (via a look-up table) and digital to analogue conversion into a single device. An on-chip phase-locked loop and pixel multiplexer means that all pixel and clock inputs to the CVC are at low frequency TTL levels.

The INMOS IMS G180 CLUT provides the output stages for very high resolution mixed true-colour and pseudo-colour graphics systems. The device combines a versatile pixel multiplexer together with three independent colour channels, each comprising two look-up tables, an overlay table and a high performance video DAC. The device also performs internal clock acceleration so that a TTL clock (at the same rate as pixel data) can be supplied. It can be configured to various pixel formats including a mode to easily mix 24 bit true-colour and 8 bit pseudo-colour images on the same screen (picture in picture).

In addition to graphics devices, the INMOS product range also includes transputer products, digital signal processing devices and fast SRAMs. For further information concerning INMOS products please contact your local SGS-THOMSON sales outlet.

Contents

1	INMOS 	
	1.1	Introduction 	
	1.2	Production 
	1.3	Quality and reliability 	
	1.4	Future developments 	
		1.4.1	Research and development 
		1.4.2	Process developments 

2	Graphics overview 	
	2.1	The advancing graphics market 
	2.2	CLUTs and colour representation 
		2.2.1	Where does a GLUT fit into a graphics system ?
	2.3	The INMOS GLUT history 
		2.3.1	The INMOS VGA compatible GLUT range 
		2.3.2	Choosing your device - functionality 
		2.3.3	Choosing your CLUT - speed selection 
		2.3.4	Colour Video Controllers 
		2.3.5	High-Performance CLUTs 

3	IMS G171 high performance colour look-up table
	3.1	Pin designations 	
		3.1.1	Pixel interface 	
		3.1.2	Analogue interface 	
		3.1.3	Microprocessor interface 	
		3.1.4	Power supply 	
		3.1.5	Internal registers 	
	3.2	Device description 	
		3.2.1	Video path 	
		3.2.2	Analogue outputs 	
		3.2.3	Microprocessor interface 	
		3.2.4	Writing to the look-up table 	
		3.2.5	Reading from the look-up table 	
		3.2.6	Asynchronous look-up table access 	
		3.2.7	The Pixel Mask register 	
	3.3	Electrical specifications 	
		3.3.1	Absolute maximum ratings 	
		3.3.2	DC operating conditions 	
		3.3.3	DAC characteristics 	
		3.3.4	AC test conditions 	
		3.3.5	Capacitance 	
		3.3.6	Video operation 	
		3.3.7	Microprocessor interface operation 	
	3.4	Designing with the IMS G171 	
		3.4.1	Board layout - general 	
		3.4.2	Power supply decoupling 	
		3.4.3	Analogue output - line driving
		3.4.4	Analogue output - protection
		3.4.5	Digital input termination 
		3.4.6	Current reference - design 
		3.4.7	Current reference - decoupling 
		3.4.8	Pixel Mask register synchronisation 
	3.5	Package specifications 
		3.5.1	28 pin dual-in-line package 	
		3.5.2	Ordering Information 	

4	IMS G176/176L high performance colour look-up table
	4.1	Pin designations 	
		4.1.1	Pixel interface 	
		4.1.2	Analogue interface 	
		4.1.3	Microprocessor interface 	
		4.1.4	Power supply 	
		4.1.5	Internal registers 	
	4.2	Device description 	
		4.2.1	Video path 	
		4.2.2	Analogue outputs 	
		4.2.3	Microprocessor interface	
			Writing to the look-up table 	
			Reading from the look-up table 	
			Asynchronous microprocessor interface access 	
			The Pixel Mask register 	
	4.3	Electrical specifications 	
		4.3.1	Absolute maximum ratings 	
		4.3.2	DC operating conditions 	
			DC electrical characteristics
		4.3.3	Power down 	
		4.3.4	DAC characteristics 	
		4.3.5	AC test conditions 	
		4.3.6	Capacitance 	
		4.3.7	Video operation 	
		4.3.8	Microprocessor interface operation 	
	4.4	Designing with the IMS G176/L 	
		4.4.1	Board layout - general 	
		4.4.2	Power supply decoupling 	
		4.4.3	Analogue output - line driving 	
			Double termination 	
			Buffered signal 	
		4.4.4	Analogue output - protection 	
		4.4.5	Digital input termination 	
		4.4.6	Current reference - design 	
		4.4.7	Current reference - decoupling 	
	4.5	Package specifications 	
		4.5.1	28 pin dual-in-line package 	
		4.5.2	32 pin plastic leaded-chip-carrier package 	
		4.5.3	44 pin plastic leaded-chip-carrier package 	
		4.5.4	Ordering information

5	IMS G178 high performance colour look-up table 	
	5.1	Pin designations 	
		5.1.1	Pixel interface 	
		5.1.2	Analogue interface 	
		5.1.3	Microprocessor interface 	
		5.1.4	Power supply 	
		5.1.5	Internal registers 	
	5.2	Device description 	
		5.2.1	Video path 	
		5.2.2	Analogue outputs 	
		5.2.3	Microprocessor interface 	
			Writing to the look-up table 	
			Reading from the look-up table 	
			Asynchronous microprocessor interface access 	
			The Pixel Mask register 	
	5.3	Electrical specifications 	
		5.3.1	Absolute maximum ratings 	
		5.3.2	DC operating conditions 	
			DC electrical characteristics 	
		5.3.3	DAC characteristics 	
		5.3.4	AC test conditions 	
		5.3.5	Capacitance 	
		5.3.6	Video operation 	
		5.3.7	Microprocessor interface operation 	
	5.4	Designing with the IMS G178 	
		5.4.1	Board layout - general 	
		5.4.2	Power supply decoupling 	
		5.4.3	Analogue output - line driving 	
		5.4.4	Analogue output - protection 	
		5.4.5	Digital input termination 	
		5.4.6	Current reference - design 	
		5.4.7	Current reference - decoupling 	
	5.5	Package specifications 	
		5.5.1	32 pin plastic leaded-chip-carrier package 	
		5.5.2	44 pin plastic leaded chip carrier package 	
		5.5.3	Ordering information 	

6	IMS G300B colour video controller
	6.1	Introduction 	
		6.1.1	Clocks 	
		6.1.2	Video timing 	
		6.1.3	Screen management 	
		6.1.4	Pixel port 	
		6.1.5	Video DACs 	
		6.1.6	Programming port 
		6.1.7	System Operation 
	6.2	Pin function reference guide 
		6.2.1	Micro port 
		6.2.2	Pixel port 
		6.2.3	Miscellaneous 
		6.2.4	Phase locked loop
		6.2.5	Video signals
		6.2.6	Supplies 	
	6.3	Register function reference guide 	
	6.4	The control register and boot location reference guide 	
	6.5	Micro port timing reference guide 	
	6.6	Pixel port timing reference guide 	
	6.7	ClockIn timing reference guide 	
	6.8	General parametric conditions and characteristics 	
		6.8.1	Absolute maximum ratings 	
		6.8.2	Operating conditions 	
		6.8.3	Operating characteristics 	
		6.8.4	Output drive capability 	
	6.9	The video timing generator 	
		6.9.1	Introduction 	
		6.9.2	The display screen 	
		6.9.3	Line timing parameters 	
		6.9.4	Frame timing parameters 	
		6.9.5	Parameter calculation 	
		6.9.6	The startup sequence 
	6.10	The G300 Address Map 
	6.11	Synchronising and Blanking signals 	
		6.11.1	Introduction 
		6.11.2	Master mode 
		6.11.3	Slave mode 
		6.11.4	Digital Blanking pin 	
	6.12	The micro port 
		6.12.1	Introduction 
		6.12.2	Initialisation 
		6.12.3	Programming operation 
		6.12.4	Byte Wide operation 
			Read cycles 
			Write cycles 
			Writing to the Control register in byte mode 
			Interaction with DMA 
		6.12.5	Byte access sequence definitions 
			Notes 
		6.12.6	The transfer address, line start and top of screen 
		6.12.7	The screen transfer operation 
		6.12.8	Transfer cycle timing 
		6.12.9	FrameInactive 
	6.13	The pixel port 
		6.13.1	Pixel port operation 
		6.13.2	Mode 1 operation 
			Colour programming in 1, 2 and 4 bits per pixel modes
			Pixel ordering 
		6.13.3	Mode 2 operation 
	6.14	The video DACs 
		6.14.1	General 	
		6.14.2	DAC output waveform 
		6.14.3	DAC characteristics 	
		6.14.4	Power supply and current reference
		6.14.5	Current reference - decoupling 
		6.14.6	Analogue output - line driving 
		6.14.7	Analogue output - protection 
	6.15	Clock generation and phase locked loop 
		6.15.1	Introduction 
		6.15.2	ClkIn 
		6.15.3	CapPlus, CapMinus 
		6.15.4	Speed selection 
		6.15.5	Recommended Input clock and multiplication factors
	6.16	Package specifications 
		6.16.1	84 pin grid array package 
		6.16.2	100 pin ceramic quad flatpack package 
		6.16.3	Ordering information 
	6.17	Programming example for Hitachi HM-4219/4119 monitor 
		6.17.1	Calculation of parameters 

7	IMS G332 colour video controller 
	7.1	Introduction 
	7.2	Pin function reference guide 
		7.2.1	Micro port 
		7.2.2	Pixel port 
		7.2.3	Miscellaneous 
	7.3	Phase locked loop 
		7.3.1	Video signals 
		7.3.2	Supplies 	
	7.4	Register function reference guide 	
	7.5	Datapath register allocation 	
			Notes 
	7.6	The control registers and boot location 	
	7.7	Micro port timing reference guide 	
	7.8	Video Timing Generator	
		7.8.1	The display screen 	
		7.8.2	Line timing parameters 	
		7.8.3	Frame timing parameters 	
		7.8.4	Parameter calculation 	
		7.8.5	The startup sequence 	
	7.9	Synchronising and blanking signals 	
		7.9.1	Introduction 	
		7.9.2	Master mode 	
		7.9.3	Slave mode 	
	7.10	The micro port 	
		7.10.1	Introduction 	
		7.10.2	Word alignment 	
		7.10.3	Micro port read/write cycles 	
		7.10.4	DMA transfer operation 	
		7.10.5	VRAM address increment 	
		7.10.6	FrameInactive 	
	7.11	The pixel port 	
		7.11.1	Interleaved/non-interleaved operation 	
		7.11.2	Pixel sampling 	
		7.11.3	Pixel multiplexing 	
			Non-interleaved mode 	
			Interleaved mode 	
		7.11.4	True colour modes (15 and 16 bits per pixel) 	
		7.11.5	Pseudo colour modes (1, 2, 4 and 8 bits per pixel)
		7.11.6	Mask register 	
	7.12	Hardware cursor 	
	7.13	Anti-sparkle colour palette 	
	7.14	Checksum registers 	
	7.15	Clocks 	
		7.15.1	PLL mode 	
		7.15.2	'Times1' mode 	
	7.16	The video DACs 	
		7.16.1	General 	
		7.16.2	DAC characteristics 	
		7.16.3	Power supply and reference circuit 	
		7.16.4	Power supply and current reference 	
		7.16.5	Current reference - decoupling 	
		7.16.6	Analogue output - line driving 	
		7.16.7	Analogue output - protection 	
	7.17	General parametric conditions and characteristics 	
		7.17.1	Absolute Maximum ratings 	
		7.17.2	Operating conditions 	
		7.17.3	Operating characteristics 	
		7.17.4	Output drive capability 	
	7.18	Package specifications 	
		7.18.1	100 pin ceramic quad flatpack package 	
		7.18.2	Ordering information 	

8	IMS G364 colour video controller 	
	8.1	Introduction 	
	8.2	Pin function reference guide 	
		8.2.1	Micro port 	
		8.2.2	Pixel port 	
		8.2.3	Miscellaneous 	
	8.3	Phase locked loop 	
		8.3.1	Video signals 	
		8.3.2	Supplies 	
	8.4	Register function reference guide 	
	8.5	Datapath register allocation 	
			Notes 
	8.6	The control registers and boot location 	
	8.7	Micro port timing reference guide 	
	8.8	Video Timing Generator 	
		8.8.1	The display screen 	
		8.8.2	Line timing parameters 	
		8.8.3	Frame timing parameters 	
		8.8.4	Parameter calculation 	
		8.8.5	The startup sequence 	
	8.9	Synchronising and blanking signals
		8.9.1	Introduction 	
		8.9.2	Master mode 	
		8.9.3	Slave mode 	
	8.10	The micro port 	
		8.10.1	Introduction 	
		8.10.2	Word alignment 	
		8.10.3	Micro port read/write cycles 	
		8.10.4	DMA transfer operation 	
		8.10.5	VRAM address increment 	
		8.10.6	FrameInactive 	
	8.11	The pixel port 	
		8.11.1	Interleaved/non-interleaved operation 	
		8.11.2	Pixel sampling 	
		8.11.3	Pixel multiplexing 	
			Non-interleaved mode 	
			Interleaved mode 	
		8.11.4	True colour modes (15, 16 and 24 bits per pixel) 	
			24 bits per pixel mode 	
			16 bits per pixel mode 	
			15 bits per pixel mode 	
		8.11.5	Pseudo colour modes (1, 2, 4 and 8 bits per pixel)
		8.11.6	Mask register 	
	8.12	Hardware cursor 	
	8.13	Anti-sparkle colour palette 	
	8.14	Checksum registers 	
	8.15	Clocks 	
		8.15.1	PLL mode 	
		8.15.2	'Times 1' mode 	
	8.16	The video DACs 	
		8.16.1	General 	
		8.16.2	DAC characteristics 	
		8.16.3	Power supply and reference circuit 	
		8.16.4	Power supply and current reference 	
		8.16.5	Current reference - decoupling 	
		8.16.6	Analogue output - line driving 	
		8.16.7	Analogue output - protection 	
	8.17	General parametric conditions and characteristics 	
		8.17.1	Absolute Maximum ratings 	
		8.17.2	Operating conditions 	
		8.17.3	Operating characteristics 	
		8.17.4	Output drive capability 	
	8.18	Package specifications 	
		8.18.1	132 pin grid array package 	
		8.18.2	Ordering information 	

9	IMS G180/G181 combined true and pseudo-colour look-up table
	9.1	Device description 	
		9.1.1	Pixel modes 
		9.1.2	Clock acceleration 
		9.1.3	Overlays 
		9.1.4	Colour Channel Architecture 
		9.1.5	Testability 
		9.1.6	The DACS and reference circuitry 
		9.1.7	Microprocessor interface 
	9.2	Pin function reference guide 
		9.2.1	Pixel interface
		9.2.2	Analogue interface 	
		9.2.3	Microprocessor interface 	
		9.2.4	Power supply 	
	9.3	Internal registers 	
		9.3.1	Accessing the LUT and overlay tables 	
		9.3.2	The pseudo-colour mask and overlay mask registers 	
		9.3.3	The pixel mode register 	
		9.3.4	The DAC control register 	
		9.3.5	Panning register 	
	9.4	Compositing control register 	
	9.5	Test checksum register 	

10 Designing with INMOS CLUTS 	
	10.1	Using INMOS CLUTs 	
		10.1.1	General board layout 	
		10.1.2	The power supply to the CLUT 	
		10.1.3	Decoupling the CLUT supply 	
		10.1.4	The pixel inputs 	
		10.1.5	The DAC outputs 	
		10.1.6	Current sources 	
		10.1.7	Current versus voltage reference comparison 	
			The INMOS recommended circuit 	
			A typical recommended voltage reference circuit	
		10.1.8	Radiated power from graphics systems 	
		10.1.9	Minimising the power dissipation of a CLUT 	
	10.2	Circuit techniques using the IMS G17X family 	
		10.2.1	Adding composite sync to the G171/6 	
	10.3	Troubleshooting - common problems and their solutions 	
		10.3.1	Unexplained colour changes on the screen 	
		10.3.2	Grey streaks on light/dark boundaries 	

11 Designing with INMOS CVCs 
	11.1	Programming the IMS G300 colour video controller 
		11.1.1	Introduction 
		11.1.2	The IMS G300 memory mapping 
		11.1.3	Host access to the IMS G300 internal registers 
		11.1.4	The internal sections of the IMS G300 
		11.1.5	The control register 	
		11.1.6	The data path registers
		11.1.7	The mask register	
		11.1.8	The boot location (phase locked loop multiplier)
		11.1.9	Colour palette 	
		11.1.10	Resetting and re-programming the IMS G300 	
		11.1.11	The effect of reset 	
		11.1.12	Initialising the IMS G300 	
		11.1.13	Re-programming the IMS G300 	
	11.2	Using the IMS G300B feature enhancements 	
		11.2.1	Introduction 	
		11.2.2	Different number of bits per pixel 	
		11.2.3	Address step control 	
		11.2.4	Blank I/O
	11.3	Moving software from the IMS G300A to the IMS G300B 	
		11.3.1	Introduction 	
		11.3.2	Differences between the revisions A and B 	
		11.3.3	Software changes required when upgrading from revision A to B
		11.3.4	Bits per pixel 	
		11.3.5	Use of the colour palette in mode 2 	
		11.3.6	Composite blank input / output 	
		11.3.7	Phase locked loop control bit 	
	11.4	Hardware design upgrading from the IMS G300A to the IMS G300B 	
		11.4.1	Introduction 	
		11.4.2	Modifying a board from the IMS G300A to accept an IMS G300B

A Quality and reliability 	
	A.1	Quality and reliability
		A.1.1	Introduction 	
		A.1.2	Quality culture 	
		A.1.3	Organisation and management 	
		A.1.4	Quality by design 	
		A.1.5	Quality auditing 	
		A.1.6	Documentation control system 
		A.1.7	Reliability assurance 

B Graphics glossary 	
	B.1	Graphics glossary

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Last modification: 09.05.2011 16:54:58