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Hardware Projects

A generic overview about my past, current and (maybe) future hardware related transputer projects.

Other interesting hardware rebuildings are done by Axel Muhr from Germany.
You can find his documented transputer projects here: [geekdot.com]



Some short facts: The adapter is based on a USB controller (CY7C68013A-56PVXC) and a Spartan II FPGA (XC2S15-5VQG100C). There are two links at 10 or 20 MHz with own subsystem up or down. The external link connector will be a dual RJ45 jack.

IMPORTANT: The technique to prevent overlapped acknowledgement occurring on the last byte of the message to avoid the T800C (05 or earlier) output bug isn't possible with the current design. A T800C connected by IMS C011 or C012 cannot fail, as these devices cannot generate overlapped acknowledgement.

The printed circuit board:

CAM Output: usblink_v1.0.pdf

PCB: PCB01.JPG PCB02.JPG PCB03.JPG PCB04.JPG PCB05.JPG

RJ45 Jack and Cable:

RJ45 FEMAL

The link signals use differential line drivers/receivers to provide maximum noise immunity. Because the signal is sent differentially common mode noise is rejected by the receiver up to its common mode rejection limit. The DS89C21 from National Semiconductor operates over 20Mbps and has a typical driver skew of 400ps and a receiver skew of 500ps. I'm sorry to say, that the maximum skew values exceeds the allowed limit of 3ns at 20MHz. Therefore is the operation at a link speed of 20MHz not guaranteed but certainly possible.

The subsystem (RAE) is implemented with open collector/drain outputs on all three signals and all three values can be read. So there is no preferred direction and the direction depends on the software usage of this signals.

The green LED's shows the link activity. The left one is for data receive and the right one for data transmit. There brightness is NOT data-sensitive.

crossover cable

This link connector permits to use standard Ethernet cables. It requires a so called 100baseTX crossover cable which has two pairs crossed and two pairs uncrossed. Depending on the used length CAT5 should be sufficient.

For testing it is possible to use a simple Ethernet loopback cable like the COMPAQ 317463-001. It's also valid to connect both RJ45 jacks with a crossover cable. This arrangement will be used to test the maximum throughput of this design. Both functions (loopback and crossback) are also available inside the FPGA and maybe there will be something like a piece of software called "cable check".

Performance:

The current implementation allows a quick performance preview. The design is currently equipped with the external loopback adapter. To get realistic values I test with a send block and receive block sequential loop, which is almost comparable with the iserver protocol. The shown values are from the I/O ReadBytes/s performance counter of my test program. The I/O WriteBytes/s counter values are identical. So from USB purposes the throughput is twofold. The green line is the maximum in loopback, because thereby is no overlapping possible. The exact value is 20/(11+2+2) MB/s. The additional 2 clock cycles are the internal delay from receiving an Acknowledge to start shifting the next Byte on the Link. The 1.33 MB/s are easily reachable with overlapped send & receive. The gray line shows the block size. There were always 10000 passes. Perfmon Screenshot

<    0Mb> .................
Using \\?\usb#vid_16c0&pid_09ce#6&d65d6ef&0&4#{66180882-47b3-4eaf-a087-143fa2daffe9} ispy 3.23 | mtest 3.22
   # Part rate Link# [  Link0  Link1  Link2  Link3 ] RAM,cycle
   0 T800d-25 1.8M 0 [   HOST    ...    ...    ... ] 4K,1 4096K,3;

IMS D7214C "Hello World" Benchmark:

The following table shows the overall execution time in seconds of the individual statement except the last line which is taken from the ispy output.

  B004PDD B008MS USB Speedup
icc hello /ta /si 2.448 2.265 1.453 1.62
ilink hello.tco /f startup.lnk /ta /si 11.992 11.968 9.562 1.25
icollect hello.lku /t /si 2.738 2.796 1.968 1.41
%iserver% /sr /ss /sc hello.btl /si 0.617 0.593 0.437 1.38
ispy.exe 291 KB/s 300 KB/s 1772 KB/s 6.00

This benchmark shows the execution time for a full compilation cycle of the hello world classic C-sample. The speedup of the USBLINK is only about 1.3 because the transfer is done in very small packages. For the icc part there are 64 packages (SP-Protocol) from and 64 to the transputer. A total of 1328 bytes have been received and 7885 bytes have been sent. This gives an average of 125.20 bytes per answer, but 42 or 66% of them are lower than 10 bytes! The distinct advance is during the image (.btl) download. I'll extend this benchmark with the B004 PCI adapter results soon. As far as I remember is this a really high-flyer.

Aalener Link Adaptor:

To connect the USBLINK to a transputer system with Aalener Link connectors (D-Sub with 9 Pins) is simple. For instance there is a customizable Adapter from CUI Inc. (AMK-0001). Only the VCC conductor must be omitted.

The B004 part is running. It's a VHDL Design for XILINX Vertex or Spartan2 FPGA's. On a PCI prototyping card full functioning.

KEK Transputerboard 64MB

In October 2006 I bought a private transputer project and many worthwhile books from Volker B. (Germany). The design was a Eurocard (100mm x 160mm) with one transputer (T805@25MHz), some simple TTL chips and four 30 pin SIMM sockets.

Schematic diagram: kek13.pdf

Four boards were assembled and five were blank. During my searching for more SIMMs I found someone in USA, who sold 60ns 16MB SIMMs. In short, I bought 36 16MB SIMMs, some TTL's, 19" front covers 6TE, sockets and so on. There was a required modification from the original design, to change the RAS-only refresh to a CAS-before-RAS refresh (with only two scratches, two short wires and a 74F32N replaced by a 74F08N!). I've ordered 3 new boards from pcb-pool and finally I have eight full populated boards with a total of 512MB.

Using 150 ispy 3.23 | mtest 3.22
   # Part rate Link# [  Link0  Link1  Link2  Link3 ] RAM,cycle
   0 T805d-25 338k 3 [    1:0    2:1    3:2   HOST ] 4K,1 65536K,3;
   1 T805g-25 1.8M 0 [    0:0    4:1    5:2    ... ] 4K,1 65536K,3;
   2 T805g-25 1.8M 1 [    4:0    0:1    6:2    ... ] 4K,1 65536K,3;
   3 T805g-25 1.8M 2 [    5:0    6:1    0:2    ... ] 4K,1 65536K,3;
   4 T805g-25 1.8M 1 [    2:0    1:1    7:2    ... ] 4K,1 65536K,3;
   5 T805g-25 1.8M 2 [    3:0    7:1    1:2    ... ] 4K,1 65536K,3;
   6 T805d-25 1.8M 2 [    7:0    3:1    2:2    ... ] 4K,1 65536K,3;
   7 T805d-25 1.8M 2 [    6:0    5:1    4:2    ... ] 4K,1 65536K,3;

The only missing thing is configurable backplane for the 19" 3HE rack.

IMS B426 Module

In my drawer there are a lot of T800D-G25S + HM514400CZ6 and waiting for a SIZE 1 TRAM board.

Not really started. But a lot of thoughts and scribble.

IMS B433 Module

In my drawer there are a lot of T222C-G20S. I'm planning to design a SIZE 3 TRAM with nine T222 each with 64KB RAM. This requires a PGA-Socket which is surface mountable and thin 32kx8 SRAM's for the bottom side.

Why SIZE 3? A 3x3 transputer grid has 12 unconnected links and a SIZE 3 TRAM has 12 external connections for links.

Not really started. But a lot of thoughts and scribble.

(TG)² ... The Great Transputer Grid

It's the place where all of my IMS B426 and IMS B433 will be running...

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Last modification: 15.12.2010 07:44:30