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F006 (IMS B431 Ethernet Tram) User Guide

December 1991
INMOS document number: 72-TRN-235-00
98 Pages

© INMOS Limited 1991.

Introduction

frontcover 72-TRN-235-00

Document structure

This document is intended as a systems developers guide to using IMS F006A with the IMS B431 Ethernet TRAM. It is split into the following chapters.

Chapter 2 describes software and hardware installations.

Chapters 3 and 4 describe the software development environment and facilities provided by the IMS F006A. Use of the IMS B431 device driver in conjunction with the procedural interface libraries is discussed, and for each library procedure a full specification is given. ANSI C and occam programmers should find that all the information required to produce application software is contained entirely within this part of the manual.

Chapter 5 provides background information on the IEEE 802.3 CSMA/CD networking standard (Ethernet). It describes packet format, addressing and the logical address and CRC algorithms. It also specifies the exact meaning and interpretation of the Ethernet statistics gathered by IMS F006A. Details of expected Ethernet performance levels are also provided.

Chapter 6 describes the IMS B431 Ethernet TRAM hardware in detail, it describes the Ethernet interface chip and how it is programmed. This section will only be of interest to programmers who wish to write their own device driver for the IMS B431 TRAM - where special requirements preclude the use of the IMS F006A software.

Conventions

Throughout this manual reference to software routines and constants provided in C and occam will be made using ANSI C syntax. Equivalent occam names may be derived by substituting occurrences of the '_' (underscore) character with a '.' (period) character as appropriate.

Background

The IMS F006A is a software support package for the IMS B431 Ethernet TRAM. It is intended for those developers wanting to construct transputer systems incorporating IEEE 802.3 Ethernet attachment, but who are not interested in the low level programming details of the Ethernet interface hardware.

The IMS F006A software consists of a device driver for the IMS B431 Ethernet TRAM and procedural interface libraries for ANSI C and occam which access the device driver via a transputer channel pair. This facilitates the creation of transputer programs to establish and engage in packet level communication on IEEE 802.3 Ethernet based local area networks (LANs).

IMS F006A is compatible with INMOS software development toolsets. Systems developers incorporate IMS F006A with their own application software using an appropriately selected toolset.

Prerequisites

In order to develop with IMS F006A the following (minimum) environment is required:

Hardware

  • IBM PC/AT or compatible personal computer
  • IMS B008 IBM PC/AT TRAM Motherboard
  • IMS B431 Ethernet TRAM (Size 2)
  • A compute TRAM such as the IMS B404 (Size 2)

Software

  • IMS D7214 ANSI C Toolset for IBM PC/AT

or

  • IMS D7205 occam 2 Toolset for IBM PC/AT

Contents

1	Introduction
	1.1	Document structure
		1.1.1	Conventions
	1.2	Background
		1.2.1	Prerequisites

2	Installation
	2.1	IMS F006A software
	2.2	IMS B431 Ethernet TRAM
	2.3	Connecting to Ethernet (10BASE5)
		2.3.1	AUI connection
		2.3.2	AUI power

3	IMS F006A overview
	3.1	Components
	3.2	IMS B431 device driver
	3.3	IMS F006A interface libraries
	3.4	Example programs and source code
	3.5	Environments 	
		3.5.1	Development Environment
		3.5.2	Target System Environment

4	IMS F006A libraries
	4.1	Interface procedures
		4.1.1	B431_Init_Normal()
		4.1.2	B431_Init_Loopback()
		4.1.3	B431_Start_Ether()
		4.1.4	B431_Tx_Packet1()
		4.1.5	B431_Tx_Packet2()
		4.1.6	B431_Reset_Stats()
		4.1.7	B431_Stop_Ether()
		4.1.8	B431_Terminate()
		4.1.9	B431_Ether_Stats()
		4.1.10	B431_Waitfor_Event()
	4.2	Diagnostic procedures
		4.2.1	B431_Internal_Loopback()
		4.2.2	B431_External_Loopback()
	4.3	IMS B431 Device Driver
		4.3.1	Debugging support
	4.4	Using B431_Load_Driver()

5	IEEE 802.3 CSMA/CD Ethernets
	5.1	IEEE 802.3 CSMA/CD Ethernets 
		5.1.1	Packet structure 
		5.1.2	CRC algorithm 
		5.1.3	Addressing 
		5.1.4	Retry algorithm 
		5.1.5	Ethernet statistics 
		5.1.6	Time domain reflectometer 
		5.1.7	Heartbeat monitor 
		5.1.8	Performance 

6	Detailed hardware description
	6.1	Data structures
		6.1.1	Buffer and descriptor ownership
		6.1.2	Data chaining
	6.2	Software structure
	6.3	Initialising
		6.3.1	The initialisation block
		6.3.2	CSR0-CSR3
		6.3.3	Summary
	6.4	Receiving
		6.4.1	The receive message descriptor
	6.5	Size and number of receive buffers
	6.6	LANCE actions during packet reception
	6.7	Receive driver actions
		6.7.1	ERR is 0
		6.7.2	ERR is 1
		6.7.3	ENP is set (and ERR is clear)
	6.8	Transmitting
	6.9	The Transmit message descriptor
		6.9.1	Transmit message descriptor 0 (TMD0)
		6.9.2	Transmit message descriptor 1 (TMD1)
		6.9.3	Transmit message descriptor 2 (TMD2)
		6.9.4	Transmit message descriptor 3 (TMD3)
	6.10	LANCE actions during transmission
		6.10.1	Failure to transmit
	6.11	A typical transmit driver
		6.11.1	BUFF and ERR are clear
		6.11.2	BUFF is set
		6.11.3	ERR is set
	6.12	Interrupts, errors and error handling
		6.12.1	Interrupt handling
		6.12.2	Errors
	6.13	Self Testing
		6.13.1	The MODE register
		6.13.2	Loopback tests
	6.14	IMS B431 TRAM engineering data
		6.14.1	Connectors and pin allocations
		6.14.2	Pin descriptions
		6.14.3	Memory Map
		6.14.4	Mechanical details

7	References

Appendices

A	Directory structure

B	Example programs
	B.1	IMS F006A example programs
		B.1.1	C Example
		B.1.2	occam Example


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