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The Transputer Handbook

Prentice Hall International (UK) Ltd
ISBN-10: 0-13-929134-2
208 Pages

Preface

frontcover 0-13-929134-2

In this book we describe the software and hardware implementation of transputer parallel processing systems. We hope to bring together information from a multitude of sources in a more readily accessible form.

This book is not intended as a substitute for a study of engineering data when detailed design decisions are to be made, but should act as a guide to the capabilities of the transputer family and transputer-based systems. This should help the reader to choose the software and hardware solution that will best suit their problem.

Neither of us is an employee of INMOS Ltd, but we are both transputer users by choice, one in an academic environment, the other as head of a research-oriented software development company. Thus our opinions are our own, and do not always coincide with those of INMOS, and at times may be directly opposed. Despite this we would like to acknowledge the help provided by INMOS in the preparation of this book.

We would like to thank the following for permission to reproduce diagrams in the book: INMOS for Figures 2.1, 7.1-7.10, 8.1, 8.7-8.10 and 9.6; Meiko for Figure 8.11; and Parsytec GmbH for Figures 8.6 and 8.13-8.15.

The majority of our programming examples are in C, rather than occam, and we assume that the reader has a knowledge of C.

One of us (I.D.G.) thanks the University of Bath for a Visiting Fellowship, during the tenure of which this book was completed. We would also acknowledge the help provided by those transputer hardware and software manufacturers whose products are mentioned in the text.

Shepton Mallet
1990

I.D.G.
T.J.K.

Contents

	Preface
	Notational Conventions
	Trademarks

1	Introduction
	1.1 Why more power?
	1.2 How do we get more power?
	1.3 Types of parallel computer
	1.4 MIMD architectures
		1.4.1 Shared-memory machines
		1.4.2 Distributed-memory machines
	1.5 The transputer

2	The Transputer
	2.1 Microprocessor architectures
	2.2 Transputer architecture
		2.2.1 The process scheduler
		2.2.2 Communications
		2.2.3 Interrupts
		2.2.4 Memory
		2.2.5 System services
	2.3 The transputer family
		2.3.1 Sixteen-bit transputers
		2.3.2 Thirty-two-bit transputers
		2.3.3 Future transputers

3	The Instruction Set
	3.1 The evaluation stack
	3.2 Simple instructions
	3.3 Encoding
	3.4 Further instructions
	3.5 Position-independent code
	3.6 Flow of control
	3.7 Process scheduling
	3.8 Channels
	3.9 Timer
	3.10 Alternation
	3.11 Error handling
	3.12 The extended instruction set
	3.13 Graphics support
	3.14 Floating-point support
	3.15 Debugging instructions
	3.16 Processor identification

4	Low-Level Programming
	4.1 Linking code
	4.2 Code generation issues
	4.3 Bootstrapping
	4.4 Debugging
	4.5 A disassembler

5	Transputer Languages
	5.1 Occam
		5.1.1 Processes
		5.1.2 Process sequences
		5.1.3 Parallel processes
		5.1.4 Alternatives
		5.1.5 Guards
		5.1.6 Arrays of processes
		5.1.7 Channel protocols
		5.1.8 Timers
		5.1.9 Placement
		5.1.10 Configuration
	5.2 Runtime library support for parallelism in C
		5.2.1 Creating threads
		5.2.2 Inter-process communication
		5.2.3 Semaphores
		5.2.4 Alternation
		5.2.5 Configuration
	5.3 Adding parallel syntax to C
		5.3.1 Concurrent execution
		5.3.2 Channel pseudo-variables
		5.3.3 Timers
		5.3.4 Alternation

6	Software Environments
	6.1 Express
	6.2 Linda
	6.3 Trollius
	6.4 Mach
	6.5 Meikos
	6.6 Helios
	6.7 UNIX

7	Transputer Family Hardware
	7.1 Hardware architecture
		7.1.1 Floating-point unit
		7.1.2 Links
		7.1.3 Memory
		7.1.4 Error signals
		7.1.5 Event handling
		7.1.6 Reset, analyse and bootstrapping
		7.1.7 Clocking
	7.2 The transputer processors
		7.2.1 The 16-bit transputers
		7.2.2 The 32-bit transputers
	7.3 Transputer support devices
		7.3.1 Link adaptors
		7.3.2 C011 Mode 1
		7.3.3 C011 Mode 2 and C012
		7.3.4 The C004 link switch

8	System Integration
	8.1 Connecting transputer links
		8.1.1 Link data rate
		8.1.2 Matching
		8.1.3 Link buffering
		8.1.4 Optical fibers
	8.2 Reset, analyse and error schemes
		8.2.1 Subsystem reset
		8.2.2 Distributed reset
		8.2.3 Bus systems
	8.3 Transputer modules and motherboards
		8.3.1 Module architecture
		8.3.2 Typical TRAMs
		8.3.3 Motherboards
	8.4 PC and other boards
		8.4.1 PC boards
		8.4.2 Other boards
	8.5 Workstations
		8.5.1 The Atari Transputer Workstation
		8.5.2 Cogent Research
	8.6 Large-scale transputer systems
		8.6.1 The Meiko Computing Surface
		8.6.2 The Supernode
		8.6.3 Parsytec Supercluster series

9	Transputer Hardware Design
	9.1 Sixteen-bit transputer memory interface
	9.2 Thirty-two bit programmable memory interface
		9.2.1 Read and write cycles
		9.2.2 Programmable strobes
		9.2.3 DMA
	9.3 Design example - a size 2 TRAM
		9.3.1 Initial design
		9.3.2 System services and links
		9.3.3 Memory design

A	Instruction Set Reference
		Constants
		Prefix, operate and direct functions
		Prefix
		Operate
		Direct
		Arithmetic/logical instructions
		Long arithmetic instructions
		General instructions
		Two-dimensional block move instructions
		CRC and bit manipulation instructions
		Indexing/array instructions
		Timer instructions
		Input/output instructions
		ALT instructions
		Flow of control instructions
		Scheduling instructions
		Error handling instructions
		Processor initialization instructions
		Debugger support instructions
		Floating-point support instructions
		Floating-point instructions
		Entry code and miscellaneous instructions
		Load/store instructions
		Arithmetic instructions
		Rounding mode instructions
		Comparison instructions
		Conversion instructions
		Error-handling instructions

B	Memory Configuration Program

C	Product list
		Compute-only TRAMs
			INMOS
			Transtec
		Special application TRAMs
			Graphics
			Ethernet
			SCSI
			ROM
			GPIB
			Link interface
			Other
		PC boards
			Cesius
			INMOS
			Transtech
			Microway
			Parsytec
			Quintek
			Sang
			Gemini
		VME and Sun
			INMOS
			Meiko
			Transtech
			Parsytec
		HP
			Protek
		PS/2
			Parsytec
			Quintek
		Apple Macintosh
			Levco
			Parsytec
		Digital Equipment Q-bus
			Caplin
			Parsytec
		NEC-PC
			INMOS
		Acorn Archimedes
			Gnome
		Non-bus
			INMOS
			Transtech
			Parsytec
		Workstation makers
			Atari
			Cogent
			Thema
		Large-scale system makers
		Company Addresses

References and Bibliography

Index

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Last modification: 27.11.2020 18:48:18