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Digital Signal Processing Databook

First Edition 1989
INMOS document number: 72-TRN-211-00
294 Pages

© INMOS Limited 1989. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.

Preface

frontcover 72-TRN-211-00

Digital Signal Processing is a significant area of application for INMOS devices. The INMOS Digital Signal Processing Databook has been published in response to the growing interest and requests for information concerning INMOS DSP devices.

The databook comprises an overview, engineering data and applications information for the IMS A100, A110 and A121 Digital Signal Processing devices.

The INMOS Digital Signal Processing family is a range of algorithm specific devices designed to provide high performance, cost effective solutions to signal processing problems. The summary of current devices is shown below.

In addition to DSP devices, the INMOS product range also includes transputer products, graphics devices and fast SRAMS. For further information concerning INMOS products please contact your local INMOS sales outlet.

Table 1
Part Algorithm Order of
calculation
Data rate
MHz
MOPS Military
available
A100-171D convolution 32 2.125-8.568-272 yes
A100-211D convolution 32 2.5-10 80-320 yes
A100-301D convolution 32 3.75-15 120-480yes
A110-201D/2D convolution 21x1, 7x320 420  
 A121-20  2D DCT/IDCT / Filter 8x8 20 320  

Contents

	Preface

1	INMOS
	1.1	Introduction
	1.2	Manufacturing
	1.3	Assembly
	1.4	Test
	1.5	Quality and Reliability
	1.6	Military
	1.7	Future Developments
		1.7.1	Research and Development
		1.7.2	Process Developments

2	Digital signal processing overview
	2.1	Introduction
	2.2	The INMOS solution
	2.3	The IMS A100 Cascadable Signal Processor
			Radar and sonar systems
			Communications
	2.4	The IMS A110 Image and Signal Processor
			Machine	vision
			Image compression
			Contrast enhancement
			Other applications
	2.5	The IMS A121 2-D Discrete Cosine Transform Image Processor
			Image compression
			Image understanding

3	IMS A100 Cascadable signal processor
	3.1	INTRODUCTION
	3.2	DESCRIPTION
	3.3	PIN DESIGNATIONS
		3.3.1	System services
			Power
			CLK
			/RESET
			/ERROR
			BUSY
		3.3.2	Synchronous input/output
			GO
			DIN[0-15]
			DOUT[0-11]
			CIN[0-11]
			OUTRDY
		3.3.3	Asynchronous input/output
			/CS
			/CE
			/W
			ADR[0-6]
			D[0-15]
	3.4	REGISTER DESCRIPTION
		3.4.1	Memory map
		3.4.2	Registers
			CCR[0-31]
			UCR[0-31]
			SCR
			ACR
			TCR
			DIR
			DOL
			DOH
		3.4.3	Static control register
			Fast Output
			Coefficient Size
			Output Word Selection
			Continuous Swap
			Input Data Source
			Master not Slave
		3.4.4	Active control register
			Cascade Adder Overflow
			Selector Overflow
			Initiate Bank Swap
		3.4.5	Test control register
			Examine Full Output Word
	3.5	DEVICE APPLICATIONS
		3.5.1	Filtering and adaptive filtering
		3.5.2	Convolution and correlation
		3.5.3	Matrix multiplication
		3.5.4	Fourier transforms
		3.5.5	Waveform synthesis
		3.5.6	General purpose accelerator
	3.6	ELECTRICAL SPECIFICATION
		3.6.1	DC electrical characteristics
			Absolute maximum ratings
			DC operating conditions
			DC characteristics
			Capacitance
		3.6.2	AC timing characteristics
			AC test conditions
			Clock
			Memory interface read cycle
			Memory interface write cycle
			Static read accesses to DOL and DOH registers
			Typical sequence - 8 bit coefficients, normal output
			Typical sequence - 8 bit coefficients, fast output
			Typical sequence - 4 bit coefficients
			Normal output timing - 8 bit coefficient case shown
			Fast output timing - 4 bit coefficient case shown
			External GO and data input timing
			Master generated GO
			Bankswap timing
			Coefficient access timing
	3.7	PACKAGE SPECIFICATIONS
		3.7.1	84 pin grid array package
			Pin grid array thermal characteristics
		3.7.2	84 pin quad ceramic package
			Quad cerpack thermal characteristics
	3.8	MILITARY STANDARD PROGRAM
	3.9	ORDERING DETAILS

4	IMS A110 Image and signal processing sub-system
	4.1	INTRODUCTION
	4.2	DESCRIPTION
	4.3	PROGRAMMABLE SHIFT REGISTERS
	4.4	MAC ARRAY
	4.5	BACKEND POST-PROCESSOR - hardware description
		4.5.1	Shifter, Cascade Adder and Rectifier
		4.5.2	Statistics Monitor
		4.5.3	Data transformation unit
		4.5.4	Data normalises
		4.5.5	Output adder
		4.5.6	Output multiplexers
	4.6	BACKEND POST-PROCESSOR - Modes Of Operation
		4.6.1	Default mode (after Reset)
		4.6.2	Cascade adder / MAC data scalar
		4.6.3	Rectification
		4.6.4	Static scaling
		4.6.5	Dynamic scaling
		4.6.6	Simple transformation
		4.6.7	Dynamic normalisation
	4.7	GLOSSARY
	4.8	PIN DESIGNATIONS
		4.8.1	System services
			Power
			CLK
			/RESET
		4.8.2	Synchronous services
			PSRin[7-0]
			PSRout[7-0]
			Cin[21-0]
			Cout[21-0]
		4.8.3	Asynchronous input/output
			/E1, /E2
			/W
			ADR[8-0]
			D[7-0]
	4.9	REGISTER DESCRIPTION
		4.9.1	Memory map
		4.9.2	Registers
			CR0a Coefficient registers bank 0a
			CR0b Coefficient registers bank 0b
			CR0c Coefficient registers bank 0c
			CR1a Coefficient registers bank 1a
			CR1b Coefficient registers bank 1b
			CR1c Coefficient registers bank 1c
			PCRA PSRA Control register
			PCRB PSRB Control register
			PCRC PSRC Control register
			SCR Static control register
			ACR Active control register
			BCR Backend configuration register
			MMB Maximum/minimum buffer
			CMM Copy MMR
			OUB Overshoot/undershoot buffer
			COU Copy OUC
			TCR Test control register
			USR Upper saturation register
			LSR Lower saturation register
			LUT Look-up table
	4.10	REGISTERS - BIT ALLOCATION
		4.10.1	PSR control registers (PCR)
		4.10.2	Static control register (SCR)
		4.10.3	Active control register (ACR)
		4.10.4	Backend control register 0 (BCR0)
		4.10.5	Backend control register 1 (BCR1)
		4.10.6	Backend control register 2 (BCR2)
		4.10.7	Backend control register 3 (BCR3)
	4.11	ELECTRICAL SPECIFICATION
		4.11.1	DC electrical characteristics
			Absolute maximum ratings
			DC operating conditions
			DC characteristics
			Capacitance
		4.11.2	AC timing characteristics
			AC test conditions
		4.11.3	Timing diagrams
			Clock Requirements
			Microprocessor Interface Read Cycle
			Microprocessor Interface Write Cycle
			Synchronous Input and Output
	4.12	PACKAGE SPECIFICATIONS
		4.12.1	100 pin grid array package
			Pin grid array thermal characteristics
	4.13	ORDERING DETAILS

5	IMS A121 2-D discrete cosine transform image processor
	5.1	OVERALL DEVICE OPERATION
		5.1.1	The fixed ROM coefficients
		5.1.2	Number formats
		5.1.3	Internal Bit-field Selectors and Rounding
		5.1.4	Overflow, Saturation and Clipping
		5.1.5	Subtraction with the DCT function
		5.1.6	Addition with the IDCT function
		5.1.7	Resetting
	5.2	DCT FUNCTION
		5.2.1	Internal number format
		5.2.2	Internal data flow
		5.2.3	The mathematical basis for the DCT
		5.2.4	DCT coefficients
		5.2.5	DCT coefficients (14 bit signed integers)
	5.3	IDCT FUNCTION
		5.3.1	Internal number format
		5.3.2	Internal data flow
		5.3.3	The mathematical basis for the IDCT
		5.3.4	IDCT coefficients
		5.3.5	IDCT coefficients (14 bit signed integers)
	5.4	FILTER FUNCTION
		5.4.1	Internal number format
		5.4.2	Internal data flow
		5.4.3	Definition of filter
		5.4.4	Filter coefficients
		5.4.5	Filter coefficients (14 bit signed integers)
	5.5	TRANSPOSER FUNCTION
		5.5.1	Internal number format and data flow
		5.5.2	Transposition coefficients
		5.5.3	Transposition coefficients (14 bit signed integers)
	5.6	PIN DESIGNATIONS
		5.6.1	System services
			Power
			CLK
		5.6.2	Synchronous input/output
			GO
			Din[11-0]
			Dout[11-0]
			Dx[11-3]
			SEL[20]
	5.7	ELECTRICAL SPECIFICATION
		5.7.1	DC electrical characteristics
			Absolute maximum ratings
			DC operating conditions
			DC characteristics
		5.7.2	A.C. timing characteristics
			Clock requirements
			Synchronous input and output (Din, Dout, Dx)
			Synchronous control (GO, SEL[2-0])
			Overall data timing
	5.8	PACKAGE SPECIFICATIONS
		5.8.1	44 pin PLCC package
			PLCC thermal characteristics
	5.9	ORDERING DETAILS

6	IMS B009 DSP system evaluation board
	6.1	The IMS 6009 Evaluation Board
	6.2	Board Description
	6.3	Programming
	6.4	Product summary
	6.5	Technical summary
	6.6	Ordering details

7	IMS D703 DSP development system
	7.1	Introduction
	7.2	Requirements
	7.3	Software Description
		7.3.1	User Applications
		7.3.2	IMS A100 Model
		7.3.3	Address Decoder
		7.3.4	IMS B009 driver
		7.3.5	IMS B009 Emulator
		7.3.6	System Controller
		7.3.7	Multi-Window MS-DOS Interface
	7.4	Host Environment
	7.5	Ordering Details

8	Digital filtering with the IMS A100
	8.1	Introduction
	8.2	From analogue to digital
	8.3	Digital filter classifications
	8.4	Digital filter design
		8.4.1	Comparison between FIR and IIR filters
		8.4.2	Basic design parameters
		8.4.3	Design techniques suitable for FIR filters
			Window method
			Frequency sampling technique
			Optimal filter design - (Remez exchange algorithm)
			Implementing FIR filters with the IMS A100
		8.4.4	The IMS A100 and IIR filters
		8.4.5	Summary of the IIR filter design techniques
			Indirect approaches for the design of IIR filters
			The direct design techniques for IIR filters
	8.5	Finite word-length considerations and problems
	8.6	Adaptive filters
	8.7	References

9	Discrete Fourier transform with the IMS A100
	9.1	Introduction
	9.2	The basic concepts of DFT
	9.3	Algorithms for efficient evaluation of DFT
	9.4	DFT algorithms suitable for the IMS A100 implementation
		9.4.1	Rader's Prime Number Transform
		9.4.2	The chirp-z transform
	9.5	Multidimensional index mapping for DFT decomposition
		9.5.1	Basic concepts of index mapping
		9.5.2	Generalisation and conditions for uniqueness
			Relatively prime case
			Common factor case
		9.5.3	Application of index mapping to DFT decomposition
			Case 1 - prime factor decomposition
			Case 2 - common factor decomposition
		9.5.4	Extension to multiple dimensions
	9.6	References

10	Correlation and convolution with the IMS A100
	10.1	Introduction
	10.2	Correlation concepts
	10.3	Convolution concepts
	10.4	Conventional hardware for time-domain evaluation of correlation
	10.5	The IMS A100 Implementation of correlation/convolution
	10.6	Decomposition of long correlations and convolutions
	10.7	2-D image convolutions with the IMS A100
	10.8	Some application examples of correlation and convolution
		10.8.1	Delay and periodicity estimation
		10.8.2	Noise reduction using correlation techniques
		10.8.3	Pulse-compression
		10.8.4	System identification using correlation
		10.8.5	The Discrete Fourier Transform (DFT)
	10.9	References

11	Complex (I & Q) processing with the IMS A100
	11.1	Introduction
	11.2	Complex correlation
	11.3	Complex convolution

12	Hardware considerations with the IMS A100
	12.1	Introduction
		12.1.1	Scope of the document
		12.1.2	Document summary
	12.2	The IMS A100 Device
		12.2.1	Pin description and constraints
			Power Supply
			Synchronous Input/Output
			Memory interface asynchronous input/output
			System control
		12.2.2	Initialisation of IMS A100s
		12.2.3	An extra selector setting using TCR
	12.3	Smaller IMS A100 systems
		12.3.1	Board Layout Constraints
		12.3.2	Memory Interface
		12.3.3	Clocking
		12.3.4	Data input
		12.3.5	Data output and output ready
		12.3.6	Master generated GO
		12.3.7	External GO
	12.4	Large IMS A100 systems
		12.4.1	How many IMS A100 devices per board?
		12.4.2	Cascading boards
		12.4.3	Board Design
			Board description
			Memory Mapping
	12.5	Higher Data Rates using multiple IMS A100 devices
		12.5.1	Principle of operation
		12.5.2	Mechanics of Operation
		12.5.3	Using the cascade adders
		12.5.4	Extensions to this technique
	12.6	Checking and debugging
		12.6.1	The Memory Interface
		12.6.2	Clock, GO and output ready
		12.6.3	Setting up SCR values
		12.6.4	Checking the data path
		12.6.5	Fault finding guide
	12.7	Conclusions
	12.8	References

13	Image processing with the IMS A100
	13.1	Introduction
		13.1.1	The aims of this document
		13.1.2	Document structure
		13.1.3	An overview of signal processing
		13.1.4	Analogue and digital conversion
		13.1.5	Techniques for digital signal processing (DSP)
		13.1.6	Overview of image processing with the IMS A100
	13.2	Practical methods of 2 dimensional convolution
		13.2.1	2-dimensional convolution
		13.2.2	Convolution template types
			Low pass filter
			Edge detection
			Laplacian filtering (edge detection)
		13.2.3	Effect of template size
	13.3	Hardware requirements for 2-D convolution
		13.3.1	The IMS A100 model
		13.3.2	IMS A100 initialisations for convolution
		13.3.3	IMS A100 coefficient placement and data flow
		13.3.4	Image scanning for a microprocessor based system
			Image scanning for 2-D convolution Implementation
			Improved image scanning for 2-D convolution
			Convolution efficiency
		13.3.5	Moderate speed image convolution
		13.3.6	Very high speed image convolution
	13.4	Conclusions
	13.5	Recent advances - the IMS A110
	13.6	Implementation of convolution on the IMS B009
		13.6.1	Frame Grabber support
		13.6.2	The IMS B009 hardware
		13.6.3	Transputer block move capability
		13.6.4	Implementation of the 2D convolution algorithm
			The IMS T414 and IMS T212
			Performance
			Image segmentation
			Thresholding and scaling using software LUT
			Transfer of Image across links
		13.6.5	The Demonstration Program
			IMS D703 Development software
			Injection of noise onto Images
			Convolution kernel file
	13.7	References

14	Cascading IMS A110s
	14.1	Introduction
	14.2	Operation of a single IMS A110
		14.2.1	One dimensional operation of an IMS A110
		14.2.2	Two dimensional operation of an IMS A110
	14.3	Fundamentals of cascading IMS A110s
	14.4	Cascading IMS A110s to produce long one dimensional filters
	14.5	Cascading IMS A110s to produce wider two dimensional filters
	14.6	Cascading IMS A110s to produce higher two dimensional filters
	14.7	Cascading IMS A110s to produce wider and higher two dimensional filters
	14.8	Cascading IMS A110s to perform multi pass filtering operations
	14.9	Cascading IMS A110s for increased data precision
		14.9.1	Increasing data precision with an external 22 bit adder
		14.9.2	Increasing data precision with an external delay line
		14.9.3	Increasing data precision with no external hardware
	14.10	Cascading IMS A110s for increased coefficient precision
		14.10.1	Increasing coefficient precision with an external 22 bit adder
		14.10.2	Increasing coefficient precision with an external delay line
		14.10.3	Increasing coefficient precision with no external hardware
	14.11	Summary

15	The IMS A110 backend post processor
	15.1	Introduction
	15.2	Description of the backend post processor
		15.2.1	Input block (shifter, cascade adder and rectifier)
		15.2.2	Statistics monitor
		15.2.3	Data conditioning unit (data transformation unit and data normalises)
			Data transformation unit
			Data normalises
		15.2.4	Output unit (output adder and output multiplexers)
			Output adder
			Output multiplexers
	15.3	Uses of the backend post processor
		15.3.1	Local area averaging
		15.3.2	Histogram equalization
		15.3.3	Edge detection and enhancement
			Edge detection
			Edge enhancement
		15.3.4	Feature recognition
		15.3.5	Changing conditions compensation
		15.3.6	Binary image processing
		15.3.7	Multilevel thresholding - image contouring
		15.3.8	Dynamic range compression
	15.4	Summary
	15.5	References

A	Quality and Reliability
	A.1	Total quality control (TQC) and reliability programme
	A.2	Quality and reliability in design
	A.3	Document control
	A.4	New product qualification
	A.5	Product monitoring programme
	A.6	Production testing and quality monitoring procedure
		A.6.1	Reliability testing
		A.6.2	Production testing
		A.6.3	Quality monitoring procedure

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