IMS M212 disk processor
INMOS document number: 72-TRN-103-02
© INMOS Limited 1988. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.
The IMS M212 is the first device in a range of intelligent peripherals in the transputer family. The device contains hardware and interface logic to control disk drives as well as a 16-bit processor with on-chip memory and communication capability, and is consistent with the INMOS transputer architecture described in the transputer architecture manual.
This manual details the product specific aspects of the IMS M212 and contains data relevant to the engineering and programming of the device.
Other information relevant to transputer products is contained in the occam programing manual (supplied with INMOS software products and available as a separate publication), and the transputer development system manual (supplied with the development system).
The examples given in this manual are outline design studies and are included to illustrate various ways in which transputers can be used. The examples are not intended to provide accurate application designs.
The following sections assume a familiarity with the arrangement and operation of disk drives and disk drive control and an appendix (A) has been provided for the reader requiring a brief overview of these topics.
This edition of the manual is dated September 4, 1987.
Preface 1 The IMS M212 Disk processor 2 Mode 1 operation 2.1 Overview 2.2 Mode 1 programming interface 2.3 Parameters 2.4 Commands 2.4.1 EndOfSequence 2.4.2 Initialise 2.4.3 ReadParameter 2.4.4 WriteParameter 2.4.5 ReadBuffer 2.4.6 WriteBuffer 2.4.7 ReadSector 2.4.8 WriteSector 2.4.9 Restore 2.4.10 Seek 2.4.11 SelectHead 2.4.12 SelectDrive 2.4.13 PollDrives 2.4.14 FormatTrack 2.4.15 Boot 2.5 Errors and reasons 2.6 Addressing and auto-increment modes 2.7 Retries 2.8 Auto-booting 2.9 Formats available in mode 1 2.10 ECC, CRC and polynomials 2.11 Initialise defaults 2.12 Hardware requirements 2.13 Disk controller access 2.14 Sample declarations and code sequences 2.15 Getting started 3 Mode 2 operation 3.1 Overview 3.2 Control code format 3.2.1 Read register 3.2.2 Write register 3.2.3 Command code (zero data) 3.2.4 Command code (single data) 3.2.5 Repeat data code 3.2.6 Multiple data code 3.3 Bus interface logic 3.4 PIA ports 3.5 Read/Write control 3.5.1 Read/write timing and control registers 3.5.2 Operation code description 3.6 Serial/parallel conversion 3.7 Parallel/serial conversion 3.8 CRC/ECC generator 3.9 ID/DATA field comparison 3.10 Data separation 3.11 Precompensation 3.12 Timeout logic 4 IMS M212 processor 4.1 IMS M212 types 4.2 IMS M212 process multiplexing 4.3 IMS M212 Error flag 4.4 IMS M212 memory map 4.5 IMS M212 timer 4.6 IMS M212 event pins 4.7 IMS M212 link placement 5 System services and processor signals 5.1 Reset 5.2 Analyse 5.3 Bootstrapping and analysis of a "failed" system 5.3.1 Bootstrapping 5.3.2 Bootstrapping from ROM 5.3.3 Bootstrapping from a link 5.3.4 Peeking and Poking 5.4 Using Error and Analyse 6 Communications 6.1 Standard transputer links 6.1.1 Link speed selection 7 Memory interface 8 Peripheral interfacing 8.1 Event process 9 Typical configurations 10 Performance 10.1 Performance overview 10.1.1 Fast multiply, TIMES 10.1.2 IMS M212 arithmetic 10.1.3 Floating point operations 10.1.4 Effect of external memory 10.2 IMS M212 speed selections 11 Physical Parameters 11.1 Absolute maximum ratings 11.2 Recommended operating conditions 11.3 DC characteristics 11.4 Measurement of AC characteristics 11.5 Connection of INMOS serial links 11.6 AC characteristics of system services 11.7 Memory interface AC characteristics 11.8 Peripheral interfacing AC characteristics 11.9 Disk Interface Parameters 12 IMS M212 signal summary 12.1 Signal list 13 Package 13.1 J-Lead chip carrier 13.2 Pin Grid Array 13.3 Package Dimensions
A Disk drive overview B Disk controller registers C Correction algorithms for ECC's C.1 Normal correction C.2 Reverse correction C.3 Chinese correction D Data separation phase locked loop D.1 Basic Equations D.2 Typical Winchester Example D.3 Typical Floppy Example E Precompensation phase locked loop E.1 Basic Equations E.2 Typical Example F Mode 1 quick reference