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T9000 Transputer Products Overview Manual

First Edition 1991
INMOS document number: 72-TRN-228-00
208 Pages

© INMOS Limited 1991. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.


frontcover 72-TRN-228-00

The T9000 Transputer Products Overview Manual introduces the latest member of the transputer range of. microprocessors, the IMS T9000. Transputers are designed to provide extremely high performance in single processor applications and are also designed with hardware and software features for the construction of multiprocessing systems.

Other transputer products include the IMS T225, a 16 bit microprocessor, the 32 bit IMS T425 and the IMS T8xx series, which are 32 bit microprocessors with an on-chip 64 bit floating point processor. Details of these and their support devices can be found in The Transputer Databook, which is available as a separate publication. Other transputer related documents, including various application and technical notes, are also available from INMOS.

This manual consists of two parts; an overview section and a set of more detailed documents for the first members of the new product range. Part 1, the overview, introduces the transputer architecture and then the features and benefits of the IMS T9000 family. Part 2 contains preliminary information on the IMS T9000 transputer, the IMS C104 packet routing switch and the IMS C100 system protocol converter. This is advance information and is subject to change.

More detailed documentation on the IMS T9000 family is in preparation. This will include a hardware reference manual, a programmers reference manual, a system networking manual and various application notes. Documentation for systems and software products will also be updated to reflect added support for the IMS T9000. For the latest information, contact your local SGS-THOMSON sales outlet.

Software and hardware examples given in this book are outline design studies and are included to illustrate various ways in which transputers can be used. The examples are not intended to provide accurate application designs.

In addition to transputer products the INMOS product range also includes development systems, systems products and high performance graphics devices. For further information regarding INMOS products please contact your local SGS-THOMSON sales outlet.



Part 1: Product Family Overview

1	Introducing the INMOS IMS T9000 family
	1.1	Performance
	1.2	Multiprocessing
	1.3	Communications support devices
	1.4	Software
	1.5	Applications

2	The IMS T9000 transputer
	2.1	Overview
			Hierarchical memory system
			Communications system
			Multiple internal buses
			System services
	2.2	The transputer architecture
	2.3	Support for concurrent processes
	2.4	Pipelined, superscalar implementation
			The pipeline
			Grouping of instructions
			Improvements over IMS T805
	2.5	Hierarchical memory system
		2.5.1	Main cache
			Cache operation
			Use as on-chip RAM
		2.5.2	Workspace cache
			Cache operation

3	Simplicity of system design
	3.1	Single 5MHz clock input
	3.2	Programmable memory interface
	3.3	Control links and configuration
	3.4	Loading and bootstrapping
	3.5	Examples

4	Protection and error handling
	4.1	Error handling
	4.2	Protected mode
			Protected mode processes
			Executing illegal instructions
			Memory management

5	Support for multiprocessing
			Fast interrupt response and process switch
	5.1	The transputer model of concurrency
			Processes and channels
			Program structure
			Multiprocessor programs
	5.2	Other models of concurrency
			Shared memory
	5.3	Hardware scheduler
	5.4	Interrupts, events and timers
	5.5	Shared resources

6	Communication links
	6.1	Using links between transputers
	6.2	Advantages of using links
			Hardware independence
	6.3	IMS T9000 links
		6.3.1	Virtual channels
			Virtual links
			Sending packets
			Receiving packets
			The virtual channel processor
		6.3.2	Levels of link protocol
			Packet level protocol
			Token level protocol
			Bit level protocol

7	Network communications
	7.1	Message routing
			Advantages for the programmer
			Separating routers and processors
			Parallel networks
	7.2	The IMS C104
			Wormhole routing
			Minimizing routing delays
			Control links
		7.2.1	Using IMS T9000s with IMS C104s
			Header deletion
			Routing control channels
	7.3	Routing algorithms
		7.3.1	Labelling networks
		7.3.2	Avoiding deadlock

8	Other communications devices
	8.1	Mixing transputer types: the IMS C100
	8.2	Interfacing to peripherals and host systems

9	Software and systems
	9.1	Development software
		9.1.1	Configuration tools
			Hardware description
			Software description
			Mapping software to hardware
			Configuration languages
			Types of networks
		9.1.2	Initializing and loading a network
			Levels of initialization
			Booting a system from link
			Booting a system from ROM
		9.1.3	Host servers
		9.1.4	Debugging
		9.1.5	IMS T805 emulation
	9.2	iq Systems products
		9.2.1	IMS T9000 products
			Compatible development products
			IMS T9000 specific products
			Host interfaces
10	References

Part 2: Product Family Preliminary Information

IMS T9000 transputer

1	Introduction

2	Preliminary pin designations

3	Processor
	3.1	Registers
	3.2	Processes and concurrency
	3.3	Priority
	3.4	Process types
		3.4.1	G-processes: global trap-handling and debugging
		3.4.2	L-processes: local error handling and debugging
	3.5	Timers
	3.6	Block move
	3.7	Semaphores

4	Communications, events and resources
	4.1	Efficient variable-length communications
	4.2	Processor-to-processor communications
	4.3	Virtual link control blocks
		4.3.1	Errors
	4.4	VCP and CPU configuration registers
		4.4.1	MemStart register
		4.4.2	Minimum invalid virtual channel register
		4.4.3	External resource channel base register
		4.4.4	Header area base register
		4.4.5	Header offset register
		4.4.6	Packet header limit registers
		4.4.7	VCP command register
		4.4.8	VCP status register
		4.4.9	VCP link mode register
		4.4.10	Event mode register
	4.5	Events
	4.6	Resources

5	Memory management
	5.1	Protection, stack extension, and logical to physical address translation
	5.2	Regions
	5.3	Region descriptors
	5.4	Machine registers
	5.5	Debugging

6	Main Cache
	6.1	Cache instructions
	6.2	Cache configuration registers

7	Programmable memory interface
	7.1	Pin functions
		7.1.1	ProcClockOut
		7.1.2	MemData0-63
		7.1.3	MemAdd2-31
		7.1.4	notMemWrB0-3
		7.1.5	notMemRAS0-3
		7.1.6	notMemCAS0-3
		7.1.7	notMemPS0-3
		7.1.8	MemWait
		7.1.9	MemReqIn, MemGranted
		7.1.10	MemReqOut
		7.1.11	notMemBootCE
		7.1.12	notMemRf
	7.2	External Bus Cycles
		7.2.1	External DRAM cycles
		7.2.2	External non-DRAM cycles
		7.2.3	Bank switching
	7.3	PMI configuration registers
		7.3.1	Bank address registers
			Address registers
			Mask registers
			RAS bits registers
			Format control registers
			BootSpace allocation
		7.3.2	Strobe timing registers
			Strobe registers
			Timing control registers
			Refresh control register
8	Data/Strobe links
	8.1	Low-level flow control
	8.2	Link speeds
	8.3	Errors on links
	8.4	Link configuration registers

9	Control links
	9.1	Initialization
	9.2	Commands
	9.3	Errors on control links
	9.4	Stand alone mode
	9.5	Link speed
	9.6	Control link configuration registers

10	Levels of reset and the configuration space
	10.1	Reset Levels
		10.1.1	Level 0 - hardware reset
		10.1.2	Level 1 - labelled control network
		10.1.3	Level 2 - configured network
		10.1.4	Level 3 - booted network
		10.1.5	Loading code
	10.2	Configuration space

11	Instruction set
	11.1	Direct functions
	11.2	Prefix functions
	11.3	Indirect functions
	11.4	Efficiency of encoding
	11.5	Interaction of the processor pipeline and the instruction set
	11.6	Floating point instructions
	11.7	Instruction characteristics

12	Performance
	12.1	Integer operations
	12.2	Floating point operations
	12.3	Predefines

13	Compatibility with the IMS T805
	13.1	Binary code compatibility
	13.2	Source level compatibility
	13.3	Compatibility issues

14	Mixed T9000 and T2/T4/T8 systems
	14.1	Byte mode

15	Package specifications
	15.1	208 pin ceramic quad flat pack package dimensions
	15.2	208 pin ceramic quad flat pack thermal characteristics

16	Thermal management
			Power considerations

IMS C104 packet routing switch

1	Introduction

2	Overview
	2.1	Communication on IMS T9000 transputers

3	Operation of IMS C104 networks
	3.1	Wormhole routing
	3.2	Interval labeling
	3.3	Modular composition of networks
	3.4	Use of parallel networks
	3.5	Hot spot avoidance

4	Control of the IMS C104
	4.1	Programmable parameters
		4.1.1	Partitioning
		4.1.2	Grouped adaptive routing
	4.2	Registers

5	Control links
	5.1	Commands
	5.2	Link speeds
	5.3	Control link configuration registers

6	Data/Strobe links
	6.1	Low-level flow control
	6.2	Link speeds
	6.3	Errors on links
	6.4	Link configuration registers

7	Levels of reset
	7.1	Level 0 - hardware reset
	7.2	Level 1 - labelled control network
	7.3	Level 2 - configured network
	7.4	Level 3

8	Software
	8.1	IMS T9000 configuration tools

9	Preliminary pin designations

IMS C100 system protocol converter

1	Introduction

2	IMS C100 modes of operation
	2.1	Mode pins
	2.2	Mode 0: Enables a T9-series transputer to be used in a T2/T4/T8-series network
	2.3	Mode 1: Enables a T2/T4/T8-series system to use a T9-series subsystem
	2.4	Mode 2: Enables a T9-series system to use an existing T2/T4/T8-series subsystem
	2.5	Mode 3: Enables a T9-series system to use a T2/T4/T8-series subsystem

3	Link protocols and link protocol conversion
	3.1	T2/T4/T8 series oversampled links
	3.2	T9 series data/strobe links
		3.2.1	Byte mode
	3.3	Data protocol conversion
		3.3.1	Byte-stream conversion
		3.3.2	Packetized conversion

4	Control protocols and control protocol conversion
	4.1	T2/T4/T8 type control
	4.2	T9 type control
	4.3	Control protocol conversion
		4.3.1	RAE master control (mode 0)
		4.3.2	CLink0 master control (modes 1, 2 and 3)
		4.3.3	OS Link 0 special function

5	Links
	5.1	Data links
		5.1.1	Data link speeds
		5.1.2	DS links in modes 1, 2 and 3
	5.2	Control links
		5.2.1	Control link speeds

6	Configuration
	6.1	Configuration space
	6.2	Data DS link configuration registers
	6.3	Control link configuration registers

7	Levels of reset
	7.1	Resetting links
	7.2	Level 0 - hardware reset
	7.3	Level 1 - labelled control network
	7.4	Level 2 - configured network
	7.5	Level 3

8	Software
	8.1	Toolsets

9	Pin designations

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Last modification: 11/27/2020 8:28:52 PM