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Transputer Development and iq Systems Databook

First Edition 1989
INMOS document number: 72-TRN-219-00
391 Pages

© INMOS Limited 1989. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.


frontcover 72-TRN-219-00

Development tools and system products are important and developing areas of application for INMOS devices. The Development and Systems Databook has been published to provide detailed information on the INMOS product range.

The databook comprises an overview, engineering data and applications information for the current range of development tools and systems products.

INMOS provide a wide range of development tools including compilers, toolsets and development kits. A diverse range of software is also available. INMOS systems products provide powerful development platforms for system designers interested in high density, high performance, design simplicity and cost effectiveness.

In addition to development tools and systems products, the INMOS product range also includes transputer products, graphics devices, Digital Signal Processing (DSP) devices and fast SRAMS. For further information concerning INMOS products please contact your local sales outlet.


1	Systems products overview
	1.1	Introduction
	1.2	Innovation and Quality
	1.3	TRAMS (TRAnsputer Modules)
		1.3.1	Standard Interface
		1.3.2	Upgradeability
		1.3.3	Flexibility
		1.3.4	Evaluation
	1.4	Quality and Reliability


2	TRAnsputer Modules (TRAMs)
	2.1	IMS B416 TRAM engineering data
		2.1.1	Introduction
		2.1.2	Pin descriptions
		2.1.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		2.1.4	Memory configuration
		2.1.5	Mechanical details
		2.1.6	Installation
		2.1.7	Specification
		2.1.8	Ordering Information
	2.2	IMS B401 TRAM engineering data
		2.2.1	Introduction
		2.2.2	Pin descriptions
		2.2.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		2.2.4 	Memory configuration
			Location of external memory
		2.2.5	Mechanical details
		2.2.6	Installation
		2.2.7	Specification
		2.2.8	Ordering Information
	2.3	IMS B411 TRAM engineering data
		2.3.1	Description
		2.3.2	Pin descriptions
		2.3.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		2.3.4	Memory configuration
		2.3.5	Mechanical details
		2.3.6	Installation
		2.3.7	Specification
		2.3.8	Ordering Information
	2.4	IMS B404 TRAM engineering data
		2.4.1	Introduction
		2.4.2	Pin descriptions
		2.4.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		2.4.4	Subsystem signals
		2.4.5	Memory configuration
			Location of external memory
			Subsystem register locations
		2.4.6	Mechanical details
		2.4.7	Installation
		2.4.8	Specification
		2.4.9	Ordering Information
	2.5	IMS B417 TRAM engineering data
		2.5.1	Introduction
		2.5.2	Pin descriptions
		2.5.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		2.5.4	Subsystem signals
		2.5.5	Memory configuration
			Location of external memory
			Subsystem register locations
		2.5.6	Mechanical details
		2.5.7	Installation
		2.5.8	Specification
		2.5.9	Ordering Information
	2.6	IMS B405 TRAM engineering data
		2.6.1	Introduction
		2.6.2	Pin descriptions
		2.6.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		2.6.4	Subsystem signals
		2.6.5	Memory configuration
			Location of external memory
			Subsystem register locations
			Memory parity
		2.6.6	Installation
		2.6.7	Mechanical details
		2.6.8	Specification
		2.6.9	Ordering Information
	2.7	IMS B410 TRAM engineering data
		2.7.1	Description
		2.7.2	Pin descriptions
		2.7.3	Standard TRAM signals
			notError (pin 11)
			LinkSpeedA and LinkSpeedB (pins 6 and 7)
			Link signals
		2.7.4	Memory configuration
		2.7.5	Mechanical details
		2.7.6	Installation
		2.7.7	Specification
		2.7.8	Ordering Information
	2.8	IMS B415 TRAM product overview
	2.9	IMS B418 flash-ROM TRAM product overview
		2.9.1	Specification
		2.9.2	Ordering Information
	2.10	IMS B407 TRAM engineering data
		2.10.1	Transputer Modules (TRAMs)
		2.10.2	Pin descriptions
		2.10.3	Ethernet Capabilities
			Connecting to Ethernet (10BASE5)
			Connecting to Cheapernet (10BASE2)
		2.10.4	Memory Map
		2.10.5	Using the IMS B407
		2.10.6	Mechanical details
		2.10.7	Installation
		2.10.8	Specification
		2.10.9	Ordering Information
	2.11	IMS B421 GPIB TRAM product overview
	2.12	IMS B422 SCSI TRAM product overview
	2.13	IMS B408 TRAM engineering data
		2.13.1	Introduction
		2.13.2	Pin descriptions
		2.13.3	Pixel Port signals
			Electrical Specification
		2.13.4	Memory Map
		2.13.5	Pixel Port control registers
		2.13.6	Mechanical details
		2.13.7	Installation
		2.13.8	Specification
		2.13.9	Ordering Information
	2.14	IMS B409 TRAM engineering data
		2.14.1	Introduction
		2.14.2	Pin descriptions
		2.14.3	Pixel Bus connectors
		2.14.4	The Pixel channels
			8 bits/pixel mode
			18 bits/pixel mode
			The colour look-up tables
			Video Outputs
		2.14.5	Memory Map
			Pixel Channel Mode select
			The video timing generator
			The Colour look-up tables
		2.14.6	Mechanical details
		2.14.7	Installation
		2.14.8	Specification
		2.14.9	Ordering Information
	2.15	IMS B419 TRAM engineering data
		2.15.1	Introduction
		2.15.2	Screen sizes
		2.15.3	Pin descriptions
		2.15.4	Memory Map
			SubSystem registers
		2.15.5	IMS G300 clock selection
		2.15.6	Jumper selection
		2.15.7	Video and sync outputs
		2.15.8	Mechanical details
		2.15.9	Installation
		2.15.10	Specification
		2.15.11	Ordering Information
	2.16	IMS B420 VECTRAM product overview
		2.16.1 Specification
		2.16.2 Ordering Information

3	Standard interface boards
	3.1	IMS B008 IBM PC Module Motherboard product overview
		3.1.1	Product Overview
		3.1.2	TRAM Slots
		3.1.3	System Services
		3.1.4	Link Configuration
		3.1.5	IBM PC Bus interface
		3.1.6	Link Speeds
		3.1.7	Technical Summary
		3.1.8	Ordering Information
	3.2	IMS B011 Tranputer VMEbus Master Card product overview
		3.2.1	Processor
		3.2.2	Booting
		3.2.3	Interrupts
		3.2.4	Memory
		3.2.5	VMEbus Interface
		3.2.6	R5232 ports
		3.2.7	TRAM slots
		3.2.8	Ordering Information
	3.3	IMS B014 VMEbus Module Motherboard product overview
		3.3.1	VMEbus Interface
		3.3.2	Interrupts
		3.3.3	IMS C004 Control
		3.3.4	System Services Organisation
		3.3.5	Technical Summary
		3.3.6	Ordering Information
	3.4	IMS B016 VMEbus master/slave Motherboard product overview
		3.4.1	General description
		3.4.2	Ordering Information
	3.5	IMS B015 Module Motherboard product overview
		3.5.1	Link connections
		3.5.2	Link speed selection
		3.5.3	System Services
		3.5.4	Up, Down, and Subsystem
		3.5.5	PC interface
		3.5.6	IO Address
		3.5.7	Reset, Analyse and Error registers
		3.5.8	Interface link
		3.5.9	External power supplies
		3.5.10	External Connections
		3.5.11	Specification
		3.5.12	Ordering Information
	3.6	IMS B012 Double Eurocard Motherboard engineering data
		3.6.1	Introduction
		3.6.2	Hardware Description
			Link Connections
			P1 Links
			Switch Configuration Transputer
			Reset, Analyse and Error
			Link Termination
			Error Lights
			User Power Connector
			Uncommitted Pins
		3.6.3	Ordering Information

4	Evaluation boards
	4.1	IMS B005 Double Extended Eurocard product overview
		4.1.1	Ordering Information
	4.2	IMS B009 DSP System Evaluation Board product overview
		4.2.1	The IMS B009 Evaluation Board
		4.2.2	Board Description
		4.2.3	Programming
		4.2.4	Product summary
		4.2.5	Technical summary
		4.2.6	Ordering details

Development systems

5	Software development tools
	5.1	occam 2 toolset product overview
		5.1.1	Product overview
			occam 2 development system
			Support for mixed language developments
			System building and program consistency
			Source level debugging tools
			Support for teams of developers
		5.1.2	occam 2 toolset product description
			Software tools
			Software libraries
			Programming examples
		5.1.3	D700D transputer development system support
		5.1.4	occam 2 toolset product components summary
			Software tools
			Software libraries
		5.1.5	D705 IBM PC version
			Operating requirements
			Distribution media
		5.1.6	D605 VAX VMS version
			Operating requirements
			Distribution media
		5.1.7	D505 SUN 3 version
			Operating requirements
			Distribution media
		5.1.8	Associated products
		5.1.9	Licensing information
		5.1.10	Error reporting and field support
	5.2	Parallel C compiler product overview
		5.2.1	Product overview
			Support for parallelism
			Using C with the occam 2 toolset
		5.2.2	3L Parallel C description
			Software tools
			Software libraries
		5.2.3	3L C components summary
			Software tools
			Software libraries
		5.2.4	D711 IBM PC version
			Operating requirements
			Distribution media
		5.2.5	D611 VAX VMS version
			Operating requirements
			Distribution media
		5.2.6	D511 SUN 3 version
			Operating requirements
			Distribution media
		5.2.7	Associated products
		5.2.8	Licensing information
		5.2.9	Error reporting and field support
	5.3	Parallel FORTRAN compiler product overview
		5.3.1	Product overview
			Support for parallelism
			Using FORTRAN with the occam 2 toolset
		5.3.2	3L Parallel FORTRAN description
			Software tools
			Software libraries
		5.3.3	3L FORTRAN components summary
			Software tools
			Software libraries
		5.3.4	D713 IBM PC version
			Operating requirements
			Distribution media
		5.3.5	D613 VAX VMS version
		 	Operating requirements
			Distribution media
		5.3.6	D513 SUN 3 version
			Operating requirements
			Distribution media
		5.3.7	Associated products
		5.3.8	Licensing information
		5.3.9	Error reporting and field support
	5.4	Pascal Compiler product overview
	5.5	Ada Compilers product overview
		5.5.1	Ada Compilers for the Transputer
		5.5.2	Features
		5.5.3	Recommended Configuration
			Recommended Configuration for PC mothered compiler
			Recommended Configuration for VAX hosted compiler
	5.6	IMS D700 Transputer Development System
		5.6.1	Product overview
			The user interface
			occam 2 compiler
			Loading programs into transputer networks
		5.6.2	Product description
			Software components
		5.6.3	Product components
			Integrated software components
			Software libraries
		5.6.4	D705B occam 2 toolset support
		5.6.5	Operating requirements
		5.6.6	Distribution media
		5.6.7	Licensing information
		5.6.8	Error reporting and field support

6	Board support software
	6.1	IMS S708 and IMS S514 product overview
		6.1.1	Product overview
			Support for other hosts
		6.1.2	Product components summary
			Software tools
		6.1.3	IMS S708
			Operating requirements
			Distribution media
		6.1.4	IMS S514
			Operating requirements
			Distribution media
	6.2	Ethernet Support Software product overview
		6.2.1	Product overview
		6.2.2	Product description
		6.2.3	Software components
		6.2.4	Hardware requirements
		6.2.5	Compatibility considerations
		6.2.6	Performance
		6.2.7	User Documentation
		6.2.8	Distribution media
		6.2.9	Related products

7	Transputer development kits
	7.1	Transputer Introduction Kit
	7.2	Transputer Performance Evaluation Kit
	7.3	Custom Development Kits
	7.4	IMS B211 INMOS Transputer Evaluation Module (ITEM)
		7.4.1	Introduction
		7.4.2	Applications
		7.4.3	Rear Connector Panel
		7.4.4	FCC Compliance
		7.4.5	Ordering Information


8	Dual inline transputer modules (TRAMs)
	8.1	Background
	8.2	Introduction
	8.3	Functional description
		8.3.1	Pinout of size1 module
		8.3.2	Pinout of larger sized modules
		8.3.3	TRAMs with more than one transputer
		8.3.4	Extra pins
		8.3.5	Subsystem signals driven from a TRAM
		8.3.6	Memory parity
		8.3.7	Memory map
	8.4	Electrical description
		8.4.1	Link outputs
		8.4.2	Link inputs
		8.4.3	notError output
		8.4.4	Reset and analyse inputs
		8.4.5	Clock input
		8.4.6	notError input to subsystem
		8.4.7	GND, VCC
	8.5	Mechanical description
		8.5.1	Width and length
		8.5.2	Vertical dimensions
		8.5.3	Direction of cooling
	8.6	TRAM pins and sockets
		8.6.1	Stackable socket pin
		8.6.2	Through-board sockets
		8.6.3	Subsystem pins and sockets
		8.6.4	Motherboard sockets
	8.7	Mechanical retention of TRAMs
	8.8	Profile drawings

9	Module motherboard architecture
	9.1	Introduction
	9.2	Module motherboard architecture
		9.2.1	Design goals
		9.2.2	Architecture
	9.3	Link configuration
		9.3.1	Pipeline
		9.3.2	IMS C004 link configuration
		9.3.3	T212 pipeline and 0004 control
		9.3.4	Software link configuration
	9.4	System control
		9.4.1	Reset, analyse and error
		9.4.2	Up, down and subsystem
		9.4.3	Source of control
		9.4.4	Clock
	9.5	Interface to a separate host
		9.5.1	Link interface
		9.5.2	System control interface
		9.5.3	Interrupts
	9.6	Mechanical considerations
		9.6.1	Dimensions
			Width and length
			Vertical dimensions
		9.6.2	Motherboard sockets
		9.6.3	Mechanical retention of TRAMs
		9.6.4	Module orientation
	9.7	Edge connectors

10	Some issues in scientific language application porting and farming using transputers
	10.1	Introduction
		10.1.1	Background
		10.1.2	Document notes
	10.2	Preliminary information
		10.2.1	Transputers
		10.2.2	Processes
		10.2.3	The transputer I host development relationship
		10.2.4	Why port to a transputer?
		10.2.5	Different categories of application porting
			Transputer software development tools
	10.3	Altering the application as little as possible
		10.3.1	The scenario
		10.3.2	Suitable applications
			Good candidates
		10.3.3	Identifying the best transputer for your application
		10.3.4	Some potential porting difficulties
		10.3.5	An implementation overview
		10.3.6	Porting example : SPICE
			About SPICE
		10.3.7	Porting example : TEX
		 	About TEX
		10.3.8	Further work
	10.4	Parallelizing the application
		10.4.1	Types of parallelism
		10.4.2	Why parallelize ?
		10.4.3	Definitions
		10.4.4	The stages in modularizing
		10.4.5	Modules
			Module properties
			Modules provided by the INMOS tools
			Instancing modules
			Module structure
			Module communication requirements
			Module communication protocol
		10.4.6 Guidelines on dividing an application into modules
	10.5	Implementing modules
		10.5.1	The technique
		10.5.2	Example of module implementation
		10.5.3	Implementation notes
		10.5.4	Some coding examples
		10.5.5	Software methods of increasing performance
			Good ideas
			Bad ideas
		10.5.6 Further work
	10.6	Using transputers with other processors
		10.6.1	Suitable applications
		10.6.2	Software support for mixed processor systems
			Accommodating architectural differences
			Using services provided by another processor
		10.6.3	Hardware support for mixed processor systems
		10.6.4	Communication mechanisms
			Communication by explicit polling
			Communication by explicit DMA
			Communication by device drivers
			Increasing data exchange bandwidth by software means
		10.6.5	Implementation strategy
		10.6.6	Testing strategy
		10.6.7	Further work
		10.6.8	Mixed processor example
	10.7	Farming an application
		10.7.1	Suitable applications
		10.7.2	General farm discussion
			The software components
			The farm protocol
		10.7.3	Interfacing to the farm
			Interfacing to another transputer process
			Interfacing to a process on a non-transputer processor
		10.7.4	Performance issues
			Load balancing
			General farming principles
		10.7.5	Farming part of an application
		10.7.6	Farming an entire application
			Alternative implementation
		10.7.7	Farming a heterogeneous processor application
			Alternative implementation
		10.7.8	Part port farm example : Second Sight
			About Second Sight
		10.7.9	Further work
			Flood-filling a transputer network
			Extraordinary use of transputer links
			Overcoming i/o bottlenecks
			Comparison between farms and application pipelining
			Farms of farms
			Dynamic link switching
	10.8	Planning the structure of a new application
	10.9	Summary and Conclusions
	10.10	References

11	Using the D705B occam toolset with non-occam applications
	11.1	Introduction
		11.1.1	Article notes
	11.2	Background information
		11.2.1	Transputers
		11.2.2	The transputer / host development relationship
		11.2.3	Connecting transputers together
		11.2.4	The other occam toolsets
	11.3	The INMOS scientific-language compilers
		11.3.1	The compilers
		11.3.2	Using the scientific-language compilers in the simplest case
			Building a simple C program
			Building a simple Pascal program
			Building a simple FORTRAN program
		11.3.3	Loading the tools
		11.3.4	Re-running the tools without reloading them
		11.3.5	Running transputer bootable files as MS-DOS commands
		11.3.6	The run-time libraries
		11.3.7 	Transputer memory allocation
			The occam memory allocation map
			The scientific-language memory allocation map
		11.3.8	Implementation details
			The run-time stack
			The run-time heap
			Selecting the run-time stack
			Placement of the code
			The static data area
			The scientific-language process communications interface
		11.3.9	Scientific-language channel i/o support
			C support
			Pascal support
			FORTRAN support
			Parallel C support
			Parallel FORTRAN support
		11.3.10	Additional support from Parallel C and Parallel FORTRAN
		11.3.11	Transputer assembler inserts
			Usage of assembler
			Local workspace allocation
			Review of how the transputer implements procedure calls
			The C assembler restrictions and capabilities
		11.3.12	Mixing occam and non-occam compilation units within the same process
			Parameter type compatabilities
			Hidden parameters
			Array parameters
			occam parameter supersets
			Calling an occam FUNCTION
	11.4	The INMOS D705B occam-2 toolset
		11.4.1	Software development using the D705B
		11.4.2	File naming convention
		11.4.3	Processor types
		11.4.4	Error modes
		11.4.5	The makefile generator
		11.4.6	The occam compiler
		11.4.7	The syntax checker
		11.4.8	The librarian
		11.4.9	The linker
		11.4.10	Binary listen
		11.4.11	The bootstrap tool
		11.4.12	The configures
		11.4.13	The debugger
		11.4.14	The simulator
		11.4.15	Supplementary tools
	11.5	Handling non-occam processes
		11.5.1	Equivalent occam process technology
			The Type 1 interface
			The Type 2 interface
			The Type 3 interface
		11.5.2	D705B Processor classes
		11.5.3	EOP Startup and shutdown overheads
		11.5.4	Practical considerations for writing harnesses
			Memory allocation by the standard scientific-language harness
			Writing harnesses to allocate scientific-language workspace memory
			Placing all EOP stacks below the code
			Establishing EOP workspace requirements
			Terminating the host file server
			Re-running the application without reloading
			Process priorities
	11.6	D705B debugging guidelines
		11.6.1	Problems with conventional debugging techniques
		11.6.2	Error mode considerations
		11.6.3	Run-time debugging aids.
		11.6.4	Debugging processes that are not connected to the host serves
			Overview of technique
			Implementation detail
			What to do if you don't have a debugger
	11.7	Using the D705B occam-2 toolset
		11.7.1	About makefiles
		11.7.2	Two communicating EOPs on one transputer
			Operations overview
			The root EOP
			The remote EOP
			The occam bits
			Running the program
			Re-implementation of the EOPs
		11.7.3	Two communicating EOPs on two transputers
		11.7.4	Using the debugger with the twin EOP twin transputer system
		11.7.5	Placing the EOPs in a library
		11.7.6	Sharing code amongst EOPs in a system
			The EOPs
			The shared occam code
			Linker symbol optimization
			Calculating where specific modules are placed
			Using on-chip RAM effectively
		11.7.7	Hints and tips
			Library usage guidelines
			General usage guidelines
		11.8	Some useful checklists
			11.8.1 Setting things up for the D705B
			11.8.2 What to do if a multiple EOP system won't run (on one transputer)
			11.8.3 What to do if a multiple EOP system won't run (on many transputers)
			11.8.4 A summary of performance maximization techniques
		11.9	Summary and Conclusions
		11.10	References

Quality and Reliability

A	Quality and Reliability

Cables for Board Products

B	Cables for board products

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Last modification: 11/27/2020 7:59:58 PM