Transputer Databook

Third Edition 1992
INMOS document number: 72-TRN-203-02
515 Pages

© INMOS Limited 1992. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.

Transputer product numbers

Product numbers take the following form: IMS abbbc-xyyz

IMS	= INMOS company identifier

a	= Product group

	T = Transputer
	C = Communications peripheral
	S = general software
	D = Development software
	F = Application software
	B = Motherboards and TRAMs

bbb	= Unique product identifier

	e.g. 805 = 32 bit transputer, FPU, 4K memory, 4 links.

c	= Revision code

	This is not present on all products.
	Product traceability is guaranteed by a separate lot number found elsewhere on the package.

x	= Package type

	G = PGA
	P = Plastic DIL
	S = Ceramic DIL
	J = PLCC
	F = Ceramic QFP
	P = Plastic QFP
	N = Ceramic LCC
	E = Plastic SOJ

yy	= Speed variant

z	= Specification

	S = Commercial 0-70°C
	E = Extended -55/+125°C
	I = Industrial-40/+85°C
	M = Mil Std 883C -55/+125°C

(Note: x, yy and z apply to product groups T and C only.)

	Notation and nomenclature
		Significance
		Signal naming conventions
		References
		Examples

	Transputer product numbers

1 Company overview

1	INMOS

2	SGS-THOMSON Microelectronics

3	Introduction to transputers

4	Quality and reliability

5	Military products

6	Development systems

2 Transputer architecture

1	Introduction

	1.1	Overview
			Transputers and occam
	1.2	System design rationale
		1.2.1	Programming
		1.2.2	Hardware
		1.2.3	Programmable components
	1.3	Systems architecture rationale
		1.3.1	Point to point communication links
		1.3.2	Local memory
	1.4	Communication

2	occam model
	2.1	Overview
	2.2	occam overview
		2.2.1	Processes
			Assignment
			Input
			Output
		2.2.2	Constructions
			Sequence
			Parallel
			Communication
			Conditional
			Alternation
			Loop
			Selection
			Replication
		2.2.3	Types
		2.2.4	Declarations, arrays and subscripts
		2.2.5	Procedures
		2.2.6	Functions
		2.2.7	Expressions
		2.2.8	Timer
		2.2.9	Peripheral access
	2.3	Configuration
			PLACED PAR
			PRI PAR
		2.3.1	INMOS standard links

3	Error handling

4	Program development
	4.1	Logical behavior
	4.2	Performance measurement
	4.3	Separate compilation of occam and other languages
	4.4	Memory map and placement

5	Physical architecture
	5.1	INMOS serial links
		5.1.1	Overview
		5.1.2	Link electrical specification
	5.2	System services
		5.2.1	Powering up and down, running and stopping
		5.2.2	Clock distribution
	5.3	Bootstrapping from ROM or from a link
	5.4	Peripheral interfacing

3 Transputer overview

1	Transputer internal architecture
	1.1	Registers
	1.2	Instructions
		1.2.1	Direct functions
		1.2.2	Prefix functions
		1.2.3	Indirect functions
		1.2.4	Expression evaluation
		1.2.5	Efficiency of encoding
	1.3	Support for concurrency
		1.3.1	Priority
		1.3.2	Interrupt latency
	1.4	Communications
		1.4.1	Internal channel communication
		1.4.2	External channel communication
		1.4.3	Communication links
	1.5	Timer
	1.6	Alternative
	1.7	Floating point instructions
		1.7.1	Optimizing use of the stack
		1.7.2	Concurrent operation of FPU and CPU
	1.8	Floating point unit design
	1.9	Graphics capability
		1.9.1	Example - drawing colored text

2	Conclusion

4 Transputer instruction set summary

1	Introduction
			Product identity numbers
			Floating point unit
			Notation

2	Descheduling points

3	Error instructions

4	Debugging support

5	Floating point errors for the IMS T801 and IMS T805 only

6	Block move

7	General instructions

8	Floating point instructions
	8.1	Floating point instructions for IMS T801 and IMS T805 only
	8.2	Floating point instructions for IMS T400, IMS T425 and IMS T426 only

5 Transputer performance

1	Introduction

2	Performance overview

3	Fast multiply, TIMES

4	Arithmetic

5	Floating point operations
	5.1	Floating point operations for IMS T801 and IMS T805 only
		5.1.1	Floating point functions
	5.2	Floating point operations for IMS T222 and IMS T225
	5.3	Floating point operations for IMS T400, IMS T425 and IMS T426
	5.4	Special purpose functions and procedures

6	Effect of external memory

7	Interrupt latency

6 IMS T805 transputer

1	Introduction

2	Pin designations

3	Floating point unit

4	System services
	4.1	Power
	4.2	CapPlus, CapMinus
	4.3	ClockIn
	4.4	ProcSpeedSelect0-2
	4.5	Bootstrap
	4.6	Peek and poke
	4.7	Reset
	4.8	Analyse
	4.9	Error, ErrorIn

5	Memory

6	External memory interface
	6.1	Pin functions
		6.1.1	MemAD2-31
		6.1.2	notMemRd
		6.1.3	MemnotWrD0
		6.1.4	notMemWrB0-3
		6.1.5	notMemS0-4
		6.1.6	MemWait
		6.1.7	MemnotRfD1
		6.1.8	notMemRf
		6.1.9	RefreshPending
		6.1.10	MemReq, MemGranted
		6.1.11	MemConfig
		6.1.12	ProcClockOut
	6.2	Read cycle
	6.3	Write cycle
	6.4	Wait
	6.5	Memory refresh
	6.6	Direct memory access
	6.7	Memory configuration
		6.7.1	Internal configuration
		6.7.2	External configuration

7	Events

8	Links

9	Electrical specifications
	9.1	DC electrical characteristics
	9.2	Equivalent circuits
	9.3	AC timing characteristics
	9.4	Power rating
			10 Package pinouts
	10.1	84 pin grid array package
	10.2	84 pin PLCC J-bend package
	10.3	100 pin cavity-down ceramic quad flat pack package
11	Ordering

7 IMS T801 transputer

1	Introduction

2	Pin designations

3	Floating point unit

4	System services
	4.1	Power
	4.2	CapPlus, CapMinus
	4.3	ClockIn
	4.4	ProcSpeedSelect0-2
	4.5	Bootstrap
	4.6	Peek and poke
	4.7	Reset
	4.8	Analyse
	4.9	ErrorOut

5	Memory

6	External memory interface
	6.1	Pin functions
		6.1.1	MemA2-31
		6.1.2	MemD0-31
		6.1.3	notMemCE
		6.1.4	notMemWrB0-3
		6.1.5	MemWait
		6.1.6	MemReq, MemGranted
		6.1.7	ProcClockOut
	6.2	Read cycle
	6.3	Write cycle
	6.4	Wait
	6.5	Direct memory access

7	Events

8	Links

9	Electrical specifications
	9.1	DC electrical characteristics
	9.2	Equivalent circuits
	9.3	AC timing characteristics
	9.4	Power rating

10	Package pinouts
	10.1	100 pin grid array package

11	Ordering

8 IMS T426 transputer

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapPlus, CapMinus
	3.3	ClockIn
	3.4	ProcSpeedSelect0-2
	3.5	Bootstrap
	3.6	Peek and poke
	3.7	Reset
	3.8	Analyse
	3.9	Error, ErrorIn

4	Memory

5	External memory interface
	5.1	Pin functions
		5.1.1	MemAD2-31
		5.1.2	ParityDataBit0-3
		5.1.3	ParityCheckEnable
		5.1.4	SoftParityError
		5.1.5	HardParityError
		5.1.6	ParityErrorln, ParityErrorOut
		5.1.7	notMemRd
		5.1.8	MemnotWrD0
		5.1.9	notMemWrB0-3
		5.1.10	notMemS0-4
		5.1.11	MemWait
		5.1.12	MemnotRfD1
		5.1.13	notMemRf
		5.1.14	RefreshPending
		5.1.15	MemReq, MemGranted
		5.1.16	MemConfig
		5.1.17	ProcClockOut
	5.2	Processor clock
	5.3	Strobes
	5.4	Read cycle
	5.5	Write cycle
	5.6	Parity errors
	5.7	Wait
	5.8	Memory refresh
	5.9	Direct memory access
	5.10	Memory configuration
		5.10.1	Internal configuration
		5.10.2	External configuration

6	Events

7	Links

8	Electrical specifications
	8.1	Absolute maximum ratings
	8.2	Operating conditions
	8.3	DC electrical characteristics
	8.4	Equivalent circuits
	8.5	AC timing characteristics
	8.6	Power rating

9	Package pinouts
	9.1	100 pin cavity-down ceramic quad flat pack package

10	Ordering

9 IMS T425 transputer

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapPlus, CapMinus
	3.3	ClockIn
	3.4	ProcSpeedSelect0-2
	3.5	Bootstrap
	3.6	Peek and poke
	3.7	Reset
	3.8	Analyse
	3.9	Error, ErrorIn

4	Memory

5	External memory interface
	5.1	Pin functions
		5.1.1	MemAD2-31
		5.1.2	notMemRd
		5.1.3	MemnotWrD0
		5.1.4	notMemWrB0-3
		5.1.5	notMemS0-4
		5.1.6	MemWait
		5.1.7	MemnotRfD1
		5.1.8	notMemRf
		5.1.9	RefreshPending
		5.1.10	MemReq, MemGranted
		5.1.11	MemConfig
		5.1.12	ProcClockOut
	5.2	Read cycle
	5.3	Write cycle
	5.4	Wait
	5.5	Memory refresh
	5.6	Direct memory access
	5.7	Memory configuration
		5.7.1	Internal configuration
		5.7.2	External configuration

6	Events

7	Links

8	Electrical specifications
	8.1	Absolute maximum ratings
	8.2	Operating conditions
	8.3	DC electrical characteristics
	8.4	Equivalent circuits
	8.5	AC timing characteristics
	8.6	Power rating

9	Package pinouts
	9.1	84 pin grid array package
	9.2	84 pin PLCC J-bend package
	9.3	100 pin cavity-down ceramic quad flat pack package

10	Ordering

10 IMS T400 transputer

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapPlus, CapMinus
	3.3	ClockIn
	3.4	ProcSpeedSelect0-2
	3.5	Bootstrap
	3.6	Peek and poke
	3.7	Reset
	3.8	Analyse
	3.9	Error, ErrorIn

4	Memory

5	External memory interface
	5.1	Pin functions
		5.1.1	MemAD2-31
		5.1.2	notMemRd
		5.1.3	MemnotWrD0
		5.1.4	notMemWrB0-3
		5.1.5	notMemS0-4
		5.1.6	MemWait
		5.1.7	MemnotRfD1
		5.1.8	notMemRf
		5.1.9	RefreshPending
		5.1.10	MemReq, MemGranted
		5.1.11	MemConfig
		5.1.12	ProcClockOut
	5.2	Read cycle
	5.3	Write cycle
	5.4	Wait
	5.5	Memory refresh
	5.6	Direct memory access
	5.7	Memory configuration
		5.7.1	Internal configuration
		5.7.2	External configuration

6	Events

7	Links

8	Electrical specifications
	8.1	DC electrical characteristics
	8.2	Equivalent circuits
	8.3	AC timing characteristics
	8.4	Power rating

9	Package pinouts
	9.1	84 pin PLCC J-bend package
	9.2	100 pin plastic quad flat pack
	9.3	84 pin grid array package
10	Ordering

11 IMS T225 transputer

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapPlus, CapMinus
	3.3	ClockIn
	3.4	ProcSpeedSelect0-2
	3.5	Bootstrap
	3.6	Peek and poke
	3.7	Reset
	3.8	Analyse
	3.9	Error

4	Memory

5	External memory interface
	5.1	Pin functions
		5.1.1	MemA0-15
		5.1.2	MemD0-15
		5.1.3	notMemWrB0-1
		5.1.4	notMemCE
		5.1.5	MemBAcc
		5.1.6	MemWait
		5.1.7	MemReq, MemGranted
		5.1.8	ProcClockOut
	5.2	Processor clock
	5.3	Read cycles
	5.4	Write cycles
	5.5	MemBAcc
		5.5.1	Word Read/Write in Byte Access Mode
		5.5.2	Byte Write in Byte Access Mode
			Writing a Most Significant Byte
			Writing a Least Significant Byte
	5.6	Wait
	5.7	Direct memory access

6	Events

7	Links

8	Electrical specifications
	8.1	Absolute maximum ratings
	8.2	Operating conditions
	8.3	DC electrical characteristics
	8.4	Equivalent circuits
	8.5	AC timing characteristics
	8.6	Power rating
9	Package pinouts
	9.1	68 pin grid array package
	9.2	68 pin PLCC J-bend package
	9.3	100 pin cavity-up ceramic quad flat pack (CQFP) package
10	Ordering

12 IMS T222 transputer

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapPlus, CapMinus
	3.3	ClockIn
	3.4	Bootstrap
	3.5	Peek and poke
	3.6	Reset
	3.7	Analyse
	3.8	Error

4	Memory

5	External memory interface
	5.1	ProcClockOut
	5.2	Tstates
	5.3	Internal access
	5.4	MemA0-15
	5.5	MemD0-15
	5.6	notMemWrB0-1
	5.7	notMemCE
	5.8	MemBAcc
		5.8.1	Word Read/Write in Byte Access Mode
		5.8.2	Byte Write in Byte Access Mode
			Writing a Most Significant Byte
			Writing a Least Significant Byte
	5.9	MemWait
	5.10	MemReq, MemGranted

6	Events

7	Links

8	Electrical specifications
	8.1	DC electrical characteristics
	8.2	Equivalent circuits
	8.3	AC timing characteristics
	8.4	Power rating

9	Package pinouts
	9.1	68 pin grid array package
	9.2	68 pin PLCC J-bend package

10	Ordering

13 IMS C004 programmable link switch

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapPlus, CapMinus
	3.3	ClockIn
	3.4	Reset

4	Links

5	Switch implementation

6	Applications
	6.1	Link switching
	6.2	Multiple IMS C004 control
	6.3	Bidirectional exchange
	6.4	Bus systems

7	Electrical specifications
	7.1	DC electrical characteristics
	7.2	Equivalent circuits
	7.3	AC timing characteristics
	7.4	Power rating

8	Package pinouts
	8.1	84 pin grid array package

9	Ordering

14 IMS C011 link adaptor

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapMinus
	3.3	ClockIn
	3.4	SeparateIQ
	3.5	Reset

4	Links

5	Mode 1 parallel interface
	5.1	Input port
	5.2	Output port

6	Mode 2 parallel interface
	6.1	D0-7
	6.2	notCS
	6.3	RnotW
	6.4	RS0-1
		6.4.1	Input Data Register
		6.4.2	Input Status Register
		6.4.3	Output Data Register
		6.4.4	Output Status Register
	6.5	InputInt
	6.6	OutputInt
	6.7	Data read
	6.8	Data write

7	Electrical specifications
	7.1	DC electrical characteristics
	7.2	Equivalent circuits
	7.3	AC timing characteristics
	7.4	Power rating

8	Package pinouts
	8.1	28 pin DIL package and 28 pin SOJ package pinout

9	Ordering

15 IMS C012 link adaptor

1	Introduction

2	Pin designations

3	System services
	3.1	Power
	3.2	CapMinus
	3.3	Clockin
	3.4	Reset

4	Links

5	Parallel interface
	5.1	D0-7
	5.2	notCS
	5.3	RnotW
	5.4	RS0-1
		5.4.1	Input Data Register
		5.4.2	Input Status Register
		5.4.3	Output Data Register
		5.4.4	Output Status Register
	5.5	InputInt
	5.6	OutputInt
	5.7	Data read
	5.8	Data write

6	Electrical specifications
	6.1	DC electrical characteristics
	6.2	Equivalent circuits
	6.3	AC timing characteristics
	6.4	Power rating

7	Package pinouts
	7.1	24 pin dual-in-line package

8	Ordering

A Packaging specifications

1	24 pin plastic dual-in-line (DIL) package dimensions

2	28 pin plastic dual-in-line (DIL) package dimensions

3	28 pin ceramic dual-in-line (DIL) package dimensions

4	28 pin plastic small outline J-leaded (SOJ) package dimensions

5	28 pin leadless chip carrier (LCC) package dimensions

6	68 pin grid array (PGA) package dimensions

7	68 pin plastic leadless chip carrier (PLCC) J-bend package dimensions

8	84 pin grid array (PGA) package dimensions

9	84 pin plastic leadless chip carrier (PLCC) J-bend package dimensions

10	100 pin ceramic quad flat pack (CQFP) package dimensions
	10.1	100 pin cavity-down ceramic quad flat pack
	10.2	100 pin cavity-up ceramic quad flat pack

11	100 pin plastic quad flat pack (PQFP) package dimensions

12	100 pin grid array (PGA) package dimensions

13	Package thermal characteristics

B Obsolete devices

1	Introduction

1	IMS T800 transputer
	1.1	Package specifications
		1.1.1	84 pin grid array package

2	IMS T414 transputer
	2.1	Package specifications
		2.1.1	84 pin grid array package
		2.1.2	84 pin PLCC J-bend package

3	IMS T212 transputer
	3.1	Package specifications
		3.1.1	68 pin grid array package

4	IMS M212 disk processor
	4.1	Package specifications
		4.1.1	68 pin grid array package

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