Transputer Databook
Second Edition 1989
INMOS document number: 72-TRN-203-01
604 Pages
© INMOS Limited 1989. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.
Preface
This databook describes the architecture of the transputer family of products and details some of the devices which make up that family. Items described include the 32 bit and 16 bit transputer products IMS T805, IMS T801, IMS T800, IMS T425, IMS T414, IMS T222 and IMS T225; the peripheral controller IMS M212; and the communications devices IMS C004, IMS C011 and IMS C012. For details of the military version of a device refer to The Military Micro-products Databook which is available as a separate publication.
The databook first describes the transputer architecture and general features of transputer family devices. It then continues with the various product datasheets.
A transputer is a single VLSI device with processor, memory and communications links for direct connection to other transputers. Concurrent systems can be constructed from a collection of transputers operating concurrently and communicating through links. The transputer can be used as a building block for concurrent processing systems, with occam as the associated design formalism.
Current transputer products include the 16 bit IMS T222, the 32 bit IMS T414 and IMS T425, and the IMS T800, IMS T801 and IMS T805 which are 32 bit transputers with an integral high speed floating point processor. A product preview of the IMS T225, which is a 16 bit transputer with debugger support, is also included.
The IMS M212 is an intelligent peripheral controller. It contains a 16 bit processor, on-chip memory and communications links. It contains hardware and interface logic to control disk drives and can be used as a programmable disk controller or as a general purpose peripheral interface.
The INMOS serial communication link is a high speed system interconnect which provides full duplex communication between members of the transputer family. It can also be used as a general purpose interconnect even where transputers are not used. The IMS C011 and IMS C012 link adaptors are communications devices enabling the INMOS serial communication link to be connected to parallel data ports and microprocessor buses. The IMS C004 is a programmable link switch. It provides a full crossbar switch between 32 link inputs and 32 link outputs.
The transputer development system referred to in this databook comprises an integrated editor, compiler and debugging system which enables transputers to be programmed in occam and in industry standard languages, for example, C, Fortran, Pascal. The Transputer Development System Manual is supplied with the transputer development system and is available as a separate publication.
Other information relevant to all transputer products is contained in the occam Reference Manual, supplied with INMOS software products and available as a separate publication. If more detail on the machine level operation is required, refer to Transputer Instruction Set - A Compiler Writers' Guide, which is available as a separate publication.
Various application and technical notes are also available from INMOS.
Software and hardware examples given in this databook are outline design studies and are included to illustrate various ways in which transputers can be used. The examples are not intended to provide accurate application designs.
In addition to transputer devices, the INMOS product range also includes graphics products, digital signal processing devices and memory devices. For further information concerning INMOS products, please contact your local INMOS sales outlet.
Contents
Preface Notation and nomenclature
1 INMOS
1 Introduction 1.1 Manufacturing 1.2 Assembly 1.3 Test 1.4 Quality and Reliability 1.5 Military 1.6 Future Developments 1.6.1 Research and Development 1.6.2 Process Developments
2 Transputer architecture
1 Introduction 1.1 Overview Transputers and occam 1.2 System design rationale 1.2.1 Programming 1.2.2 Hardware 1.2.3 Programmable components 1.3 Systems architecture rationale 1.3.1 Point to point communication links 1.3.2 Local memory 1.4 Communication 2 occam model 2.1 Overview 2.2 occam overview 2.2.1 Processes Assignment Input Output 2.2.2 Constructions Sequence Parallel Communication Conditional Alternation Loop Selection Replication 2.2.3 Types 2.2.4 Declarations, arrays and subscripts 2.2.5 Procedures 2.2.6 Functions 2.2.7 Expressions 2.2.8 Timer 2.2.9 Peripheral access 2.3 Configuration PLACED PAR PRI PAR 2.3.1 INMOS standard links 3 Error handling 4 Program development 4.1 Logical behaviour 4.2 Performance measurement 4.3 Separate compilation of occam and other languages 4.4 Memory map and placement 5 Physical architecture 5.1 INMOS serial links 5.1.1 Overview 5.1.2 Link electrical specification 5.2 System services 5.2.1 Powering up and down, running and stopping 5.2.2 Clock distribution 5.3 Bootstrapping from ROM or from a link 5.4 Peripheral interfacing
3 Transputer overview
1 Introduction 2 The transputer: basic architecture and concepts 2.1 A programmable device 2.2 occam 2.3 VLSI technology 2.4 Simplified processor with micro-coded scheduler 3 Transputer internal architecture 3.1 Sequential processing 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Efficiency of encoding 3.3 Support for concurrency 3.4 Communications 3.4.1 Internal channel communication 3.4.2 External channel communication 3.4.3 Communication links 3.5 Timer 3.6 Alternative 3.7 Floating point instructions 3.7.1 Optimising use of the stack 3.7.2 Concurrent operation of FPU and CPU 3.8 Floating point unit design 3.9 Graphics capability 3.9.1 Example - drawing coloured text 4 Conclusion
4 IMS T805 engineering data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Block move 3.7 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 4.3 Debugging support 4.4 Floating point errors 5 Floating point unit 6 System services 6.1 Power 6.2 CapPlus, CapMinus 6.3 ClockIn 6.4 ProcSpeedSelect0-2 6.5 Reset 6.6 Bootstrap 6.7 Peek and poke 6.8 Analyse 6.9 Error, ErrorIn 7 Memory 8 External memory interface 8.1 Pin functions 8.1.1 MemAD2-31 8.1.2 notMemRd 8.1.3 MemnotWrD0 8.1.4 notMemWrB0-3 8.1.5 notMemS0-4 8.1.6 MemWait 8.1.7 MemnotRfD1 8.1.8 notMemRf 8.1.9 RefreshPending 8.1.10 MemReq, MemGranted 8.1.11 MemConfig 8.1.12 ProcClockOut 8.2 Read cycle 8.3 Write cycle 8.4 Wait 8.5 Memory refresh 8.6 Direct memory access 8.7 Memory configuration 8.7.1 Internal configuration 8.7.2 External configuration 9 Events 10 Links 11 Electrical specifications 11.1 DC electrical characteristics 11.2 Equivalent circuits 11.3 AC timing characteristics 11.4 Power rating 12 Performance 12.1 Performance overview 12.2 Fast multiply, TIMES 12.3 Arithmetic 12.4 Floating point operations 12.4.1 Floating point functions 12.4.2 Special purpose functions and procedures 12.5 Effect of external memory 12.6 Interrupt latency 13 Package specifications 13.1 84 pin grid array package 13.2 84 pin PLCC J-bend package 13.3 84 lead quad cerpack package 14 Ordering
5 IMS T801 engineering data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Block move 3.7 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error Instructions 4.3 Debugging support 4.4 Floating point errors 5 Floating point unit 6 System services 6.1 Power 6.2 CapPlus, CapMinus 6.3 ClockIn 6.4 ProcSpeedSelect0-2 6.5 Reset 6.6 Bootstrap 6.7 Peek and poke 6.8 Analyse 6.9 ErrorOut 7 Memory 8 External memory interface 8.1 Pin functions 8.1.1 MemA2-31 8.1.2 MemD0-31 8.1.3 notMemCE 8.1.4 notMemWrB0-3 8.1.5 MemWait 8.1.6 MemReq, MemGranted 8.1.7 ProcClockOut 8.2 Read cycle 8.3 Write cycle 8.4 Wait 8.5 Direct memory access 9 Events 10 Links 11 Electrical specifications 11.1 DC electrical characteristics 11.2 Equivalent circuits 11.3 AC timing characteristics 11.4 Power rating 12 Performance 12.1 Performance overview 12.2 Fast multiply, TIMES 12.3 Arithmetic 12.4 Floating point operations 12.4.1 Floating point functions 12.4.2 Special purpose functions and procedures 12.5 Effect of external memory 12.6 Interrupt latency 13 Package specifications 13.1 100 pin grid array package 14 Ordering
6 IMS T800 engineering data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Block move 3.7 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 4.3 Floating point errors 5 Floating point unit 6 System services 6.1 Power 6.2 CapPlus, CapMinus 6.3 ClockIn 6.4 ProcSpeedSelect0-2 6.5 Reset 6.6 Bootstrap 6.7 Peek and poke 6.8 Analyse 6.9 Error, ErrorIn 7 Memory 8 External memory interface 8.1 ProcClockOut 8.2 Tstates 8.3 Internal access 8.4 MemAD2-31 8.5 MemnotWrD0 8.6 MemnotRfD1 8.7 notMemRd 8.8 notMemS0-4 8.9 notMemWrB0-3 8.10 MemConfig 8.10.1 Internal configuration 8.10.2 External configuration 8.11 notMemRf 8.12 MemWait 8.13 MemReq, MemGranted 9 Events 10 Links 11 Electrical specifications 11.1 DC electrical characteristics 11.2 Equivalent circuits 11.3 AC timing characteristics 11.4 Power rating 12 Performance 12.1 Performance overview 12.2 Fast multiply, TIMES 12.3 Arithmetic 12.4 Floating point operations 12.4.1 Floating point functions 12.4.2 Special purpose functions and procedures 12.5 Effect of external memory 12.6 Interrupt latency 13 Package specifications 13.1 84 pin grid array package 13.2 84 lead quad cerpack package 14 Ordering
7 IMS T425 engineering data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Block move 3.7 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 4.3 Debugging support 5 System services 5.1 Power 5.2 CapPlus, CapMinus 5.3 ClockIn 5.4 ProcSpeedSelect0-2 5.5 Reset 5.6 Bootstrap 5.7 Peek and poke 5.8 Analyse 5.9 Error, ErrorIn 6 Memory 7 External memory interface 7.1 ProcClockOut 7.2 Tstates 7.3 Internal access 7.4 MemAD2-31 7.5 MemnotWrD0 7.6 MemnotRfD1 7.7 notMemRd 7.8 notMemS0-4 7.9 notMemWrB0-3 7.10 MemConfig 7.10.1 Internal configuration 7.10.2 External configuration 7.11 RefreshPending 7.12 notMemRf 7.13 MemWait 7.14 MemReq, MemGranted 8 Events 9 Links 10 Electrical specifications 10.1 DC electrical characteristics 10.2 Equivalent circuits 10.3 AC timing characteristics 10.4 Power rating 11 Performance 11.1 Performance overview 11.2 Fast Multiply, TIMES 11.3 Arithmetic 11.4 Floating point operations 11.4.1 Special purpose functions and procedures 11.5 Effect of external memory 11.6 Interrupt latency 12 Package specifications 12.1 84 pin grid array package 12.2 84 pin PLCC J-bend package 12.3 84 lead quad cerpack package 13 Ordering
8 IMS T414 engineering data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 5 System services 5.1 Power 5.2 CapPlus, CapMinus 5.3 ClockIn 5.4 Reset 5.5 Bootstrap 5.6 Peek and poke 5.7 Analyse 5.8 Error 6 Memory 7 External memory interface 7.1 ProcClockOut 7.2 Tstates 7.3 Internal access 7.4 MemAD2-31 7.5 MemnotWrD0 7.6 MemnotRfD1 7.7 notMemRd 7.8 notMemS0-4 7.9 notMemWrB0-3 7.10 MemConfig 7.10.1 Internal configuration 7.10.2 External configuration 7.11 notMemRf 7.12 MemWait 7.13 MemReq, MemGranted 8 Events 9 Links 10 Electrical specifications 10.1 DC electrical characteristics 10.2 Equivalent circuits 10.3 AC timing characteristics 10.4 Power rating 11 Performance 11.1 Performance overview 11.2 Fast multiply, TIMES 11.3 Arithmetic 11.4 Floating point operations 11.5 Effect of external memory 11.6 Interrupt latency 12 Package specifications 12.1 84 pin grid array package 12.2 84 pin PLCC J-bend package 13 Ordering
9 IMS T222 engineering data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 5 System services 5.1 Power 5.2 CapPlus, CapMinus 5.3 ClockIn 5.4 Reset 5.5 Bootstrap 5.6 Peek and poke 5.7 Analyse 5.8 Error 6 Memory 7 External memory interface 7.1 ProcClockOut 7.2 Tstates 7.3 Internal access 7.4 MemA0-15 7.5 MemD0-15 7.6 notMemWrB0-1 7.7 notMemCE 7.8 MemBAcc 7.9 MemWait 7.10 MemReq, MemGranted 8 Events 9 Links 10 Electrical specifications 10.1 DC electrical characteristics 10.2 Equivalent circuits 10.3 AC timing characteristics 10.4 Power rating 11 Performance 11.1 Performance overview 11.2 Fast multiply, TIMES 11.3 Arithmetic 11.4 Floating point operations 11.5 Effect of external memory 11.6 Interrupt latency 12 Package specifications 12.1 68 pin grid array package 12.2 68 pin PLCC J-bend package 13 Ordering
10 IMS T225 preview
1 Introduction 2 Pin designations 3 Instruction set summary 4 Package specifications 4.1 68 pin grid array package 4.2 68 pin PLCC J-bend package 5 Ordering
11 IMS M212 preview
1 Introduction 1.1 IMS M212 peripheral processor 1.1.1 Central processor 1.1.2 Peripheral interface 1.1.3 Disk controller 1.1.4 Links 1.1.5 Memory system 1.1.6 Error handling 2 Operation 2.1 Mode 1 2.2 Mode 2 3 Applications 4 Package specifications 4.1 68 pin grid array package 4.2 68 pin PLCC J-bend package 5 Ordering
12 IMS C004 engineering data
1 Introduction 2 Pin designations 3 System services 3.1 Power 3.2 CapPlus, CapMinus 3.3 ClockIn 3.4 Reset 4 Links 5 Switch implementation 6 Applications 6.1 Link switching 6.2 Multiple IMS C004 control 6.3 Bidirectional exchange 6.4 Bus systems 7 Electrical specifications 7.1 DC electrical characteristics 7.2 Equivalent circuits 7.3 AC timing characteristics 7.4 Power rating 8 Package specifications 8.1 84 pin grid array package 8.2 84 lead quad cerpack package 9 Ordering
13 IMS C011 engineering data
1 Introduction 2 Pin designations 3 System services 3.1 Power 3.2 CapMinus 3.3 ClockIn 3.4 SeparateIQ 3.5 Reset 4 Links 5 Mode 1 parallel interface 5.1 Input port 5.2 Output port 6 Mode 2 Parallel interface 6.1 D0-7 6.2 notCS 6.3 RnotW 6.4 RS0-1 6.4.1 Input Data Register 6.4.2 Input Status Register 6.4.3 Output Data Register 6.4.4 Output Status Register 6.5 InputInt 6.6 OutputInt 6.7 Data read 6.8 Data write 7 Electrical specifications 7.1 DC electrical characteristics 7.2 Equivalent circuits 7.3 AC timing characteristics 7.4 Power rating 8 Package specifications 8.1 28 pin plastic dual-in-line package 8.2 28 pin ceramic dual-in-line package 8.3 28 pin SOIC package 8.4 Pinout 9 Ordering
14 IMS C012 engineering data
1 Introduction 2 Pin designations 3 System services 3.1 Power 3.2 CapMinus 3.3 ClockIn 3.4 Reset 4 Links 5 Parallel Interface 5.1 D0-7 5.2 notCS 5.3 RnotW 5.4 RS0-1 5.4.1 Input Data Register 5.4.2 Input Status Register 5.4.3 Output Data Register 5.4.4 Output Status Register 5.5 InputInt 5.6 OutputInt 5.7 Data read 5.8 Data write 6 Electrical specifications 6.1 DC electrical characteristics 6.2 Equivalent circuits 6.3 AC timing characteristics 6.4 Power rating 7 Package specifications 7.1 24 pin plastic dual-in-line package 7.2 Pinout 8 Ordering
A Quality and Reliability
A Quality and Reliability A.1 Total quality control (TQC) and reliability programme A.2 Quality and reliability In design A.3 Document control A.4 New product qualification A.5 Product monitoring programme A.6 Production testing and quality monitoring procedure A.6.1 Reliability testing A.6.2 Production testing A.6.3 Quality monitoring procedure
B Index
B Index
Back to the top