Transputer Reference Manual
First published 1988 by
Prentice Hall International (UK) Ltd
ISBN-10: 0-13-929001-X; INMOS document number: 72-TRN-006-04
362 Pages
© 1988 INMOS Limited. INMOS reserves the right to make changes in specifications at any time and without notice. The information furnished by INMOS in this publication is believed to be accurate; however, no responsibility is assumed for its use, nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted under any patents, trademarks or other rights of INMOS.
Preface
This reference manual describes the architecture of the transputer family of products and details some of the devices which make up that family. Items described include the 32 bit and 16 bit transputer products IMS T800, IMS T414 and IMS T212; the peripheral controller IMS M212; and the communications devices IMS C004, IMS C011 and IMS C012.
The manual first describes the transputer architecture and general features of transputer family devices. It then continues with the various product data sheets, followed by comparative performance details.
A transputer is a single VLSI device with processor, memory and communications links for direct connection to other transputers. Concurrent systems can be constructed from a collection of transputers operating concurrently and communicating through links. The transputer can be used as a building block for concurrent processing systems, with occam as the associated design formalism.
Current transputer products include the 16 bit IMS T212, the 32 bit IMS T414 and the IMS T800, a 32 bit transputer similar to the IMS T414 but with an integral high speed floating point processor.
The IMS M212 is an intelligent peripheral controller. It contains a 16 bit processor, on-chip memory and communications links. It contains hardware and interface logic to control disk drives and can be used as a programmable disk controller or as a general purpose peripheral interface.
The INMOS serial communication link is a high speed system interconnect which provides full duplex communication between members of the transputer family. It can also be used as a general purpose interconnect even where transputers are not used. The IMS C011 and IMS C012 link adaptors are communications devices enabling the INMOS serial communication link to be connected to parallel data ports and microprocessor buses. The IMS 0004 is a programmable link switch. It provides a full crossbar switch between 32 link inputs and 32 link outputs.
The transputer development system referred to in this manual comprises an integrated editor, compiler and debugging system which enables transputers to be programmed in occam and in industry standard languages. The Transputer Development System Manual is supplied with the transputer development system.
Other information relevant to all transputer products is contained in the occam Reference Manual, supplied with INMOS software products and available as a separate publication. Where access to transputers at machine instruction set level is necessary, the document The Transputer Instruction Set - A Compiler Writers' Guide is available.
Various application and technical notes are also available from INMOS.
Software and hardware examples given in this manual are outline design studies and are included to illustrate various ways in which transputers can be used. The examples are not intended to provide accurate application designs.
Contents
Preface Notation and nomenclature
1 Transputer Architecture
1 Introduction 1.1 Overview Transputers and occam 1.2 System design rationale 1.2.1 Programming 1.2.2 Hardware 1.2.3 Programmable components 1.3 Systems architecture rationale 1.3.1 Point to point communication links 1.3.2 Local memory 1.4 Communication 2 occam model 2.1 Overview 2.2 occam overview 2.2.1 Processes Assignment Input Output 2.2.2 Constructions Sequence Parallel Communication Conditional Alternation Loop Selection Replication 2.2.3 Types 2.2.4 Declarations, arrays and subscripts 2.2.5 Procedures 2.2.6 Functions 2.2.7 Expressions 2.2.8 Timer 2.2.9 Peripheral access 2.3 Configuration PLACED PAR PRI PAR 2.3.1 INMOS standard links 3 Error handling 4 Program development 4.1 Logical behaviour 4.2 Performance measurement 4.3 Separate compilation of occam and other languages 4.4 Memory map and placement 5 Physical architecture 5.1 INMOS serial links 5.1.1 Overview 5.1.2 Link electrical specification 5.2 System services 5.2.1 Powering up and down, running and stopping 5.2.2 Clock distribution 5.3 Bootstrapping from ROM or from a link 5.4 Peripheral interfacing
2 Transputer Overview
1 Introduction 2 The transputer: basic architecture and concepts 2.1 A programmable device 2.2 occam 2.3 VLSI technology 2.4 Simplified processor with micro-coded scheduler 2.5 Transputer products 3 Transputer internal architecture 3.1 Sequential processing 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Efficiency of encoding 3.3 Support for concurrency 3.4 Communications 3.4.1 Internal channel communication 3.4.2 External channel communication 3.4.3 Communication links 3.5 Timer 3.6 Alternative 3.7 Floating point instructions 3.7.1 Optimising use of the stack 3.7.2 Concurrent operation of FPU and CPU 3.8 Floating point unit design 3.9 Floating point performance 3.10 Graphics capability 3.10.1 Example - drawing coloured text 4 Conclusion
3 IMS T800 Engineering Data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 4.3 Floating point errors 5 Floating point unit 6 System services 6.1 Power 6.2 CapPlus, CapMinus 6.3 ClockIn 6.4 ProcSpeedSelect0-2 6.5 Reset 6.6 Bootstrap 6.7 Peek and poke 6.8 Analyse 6.9 Error, ErrorIn 7 Memory 8 External memory interface 8.1 ProcClockOut 8.2 Tstates 8.3 Internal access 8.4 MemAD2-31 8.5 MemnotWrD0 8.6 MemnotRfD1 8.7 notMemRd 8.8 notMemS0-4 8.9 notMemWrB0-3 8.10 MemConfig 8.10.1 Internal configuration 8.10.2 External configuration 8.11 notMemRf 8.12 MemWait 8.13 MemReq, MemGranted 9 Events 10 Links 11 Electrical specifications 11.1 DC electrical characteristics 11.2 Equivalent circuits 11.3 AC timing characteristics 11.4 Power rating 12 Package specifications 12.1 84 pin grid array package
4 IMS T414 Engineering Data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 5 System services 5.1 Power 5.2 CapPlus, CapMinus 5.3 ClockIn 5.4 Reset 5.5 Bootstrap 5.6 Peek and poke 5.7 Analyse 5.8 Error 6 Memory 7 External memory interface 7.1 ProcClockOut 7.2 Tstates 7.3 Internal access 7.4 MemAD2-31 7.5 MemnotWrD0 7.6 MemnotRfD1 7.7 notMemRd 7.8 notMemS0-4 7.9 notMemWrB0-3 7.10 MemConfig 7.10.1 Internal configuration 7.10.2 External configuration 7.11 notMemRf 7.12 MemWait 7.13 MemReq, MemGranted 8 Events 9 Links 10 Electrical specifications 10.1 DC electrical characteristics 10.2 Equivalent circuits 10.3 AC timing characteristics 10.4 Power rating 11 Package specifications 11.1 84 pin grid array package 11.2 84 pin PLCC J-bend package
5 IMS T212 Engineering Data
1 Introduction 2 Pin designations 3 Processor 3.1 Registers 3.2 Instructions 3.2.1 Direct functions 3.2.2 Prefix functions 3.2.3 Indirect functions 3.2.4 Expression evaluation 3.2.5 Efficiency of encoding 3.3 Processes and concurrency 3.4 Priority 3.5 Communications 3.6 Timers 4 Instruction set summary 4.1 Descheduling points 4.2 Error instructions 5 System services 5.1 Power 5.2 CapPlus, CapMinus 5.3 ClockIn 5.4 Reset 5.5 Bootstrap 5.6 Peek and poke 5.7 Analyse 5.8 Error 6 Memory 7 External memory interface 7.1 ProcClockOut 7.2 Tstates 7.3 Internal access 7.4 MemA0-15 7.5 MemD0-15 7.6 notMemWrB0-1 7.7 notMemCE 7.8 MemBAcc 7.9 MemWait 7.10 MemReq, MemGranted 8 Events 9 Links 10 Electrical specifications 10.1 DC electrical characteristics 10.2 Equivalent circuits 10.3 AC timing characteristics 10.4 Power rating 11 Package specifications 11.1 68 pin grid array package 11.2 68 pin PLCC J-bend package
6 IMS M212 Preview
1 Introduction 1.1 IMS M212 peripheral processor 1.1.1 Central processor 1.1.2 Peripheral interface 1.1.3 Disk controller 1.1.4 Links 1.1.5 Memory system 1.1.6 Error handling 2 Operation 2.1 Mode 1 2.2 Mode 2 3 Applications 4 Package specifications 4.1 68 pin grid array package 4.2 68 pin PLCC J-bend package
7 IMS C004 Engineering Data
1 Introduction 2 Pin designations 3 System services 3.1 Power 3.2 CapPlus, CapMinus 3.3 ClockIn 3.4 Reset 4 Links 5 Switch implementation 6 Applications 6.1 Link switching 6.2 Multiple IMS C004 control 6.3 Bidirectional exchange 6.4 Bus systems 7 Electrical specifications 7.1 DC electrical characteristics 7.2 Equivalent circuits 7.3 AC timing characteristics 7.4 Power rating 8 Package specifications 8.1 84 pin grid array package 9 IMS C004-A
8 IMS C011 Engineering Data
1 Introduction 2 Pin designations 3 System services 3.1 Power 3.2 CapMinus 3.3 ClockIn 3.4 SeparateIQ 3.5 Reset 4 Links 5 Mode 1 parallel interface 5.1 Input port 5.2 Output port 6 Mode 2 parallel interface 6.1 D0-7 6.2 notCS 6.3 RnotW 6.4 RS0-1 6.4.1 Input Data Register 6.4.2 Input Status Register 6.5 InputInt 6.5.1 Output Data Register 6.5.2 Output Status Register 6.6 OutputInt 6.7 Data read 6.8 Data write 7 Electrical specifications 7.1 DC electrical characteristics 7.2 Equivalent circuits 7.3 AC timing characteristics 7.4 Power rating 8 Package specifications 8.1 28 pin plastic dual-in-line package 8.2 28 pin ceramic dual-in-line package 8.3 Pinout
9 IMS C012 Engineering Data
1 Introduction 2 Pin designations 3 System services 3.1 Power 3.2 CapMinus 3.3 ClockIn 3.4 Reset 4 Links 5 Parallel interface 5.1 D0-7 5.2 notCS 5.3 RnotW 5.4 RS0-1 5.4.1 Input Data Register 5.4.2 Input Status Register 5.5 InputInt 5.5.1 Output Data Register 5.5.2 Output Status Register 5.6 OutputInt 5.7 Data read 5.8 Data write 6 Electrical specifications 6.1 DC electrical characteristics 6.2 Equivalent circuits 6.3 AC timing characteristics 6.4 Power rating 7 Package specifications 7.1 24 pin plastic dual-in-line package 7.2 Pinout
Appendices
A Performance
A.1 Performance overview A.2 Fast Multiply, TIMES A.3 Arithmetic A.4 IMS T212, IMS T414 floating point operations A.5 IMS T800 floating point operations A.5.1 IMS T800 floating point functions A.5.2 IMS T800 special purpose functions and procedures A.6 Effect of external memory A.7 Interrupt latency
B Instruction Set Summary
C Bibliography
C.1 INMOS publications C.2 INMOS technical notes C.3 Papers and extracts by INMOS authors C.4 Papers and extracts by other authors C.5 Books and monographs C.6 References
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