XGA Software Programmer's Guide

First Edition 1991
INMOS document number: 72-OEK-258-00
174 Pages

Preface

The XGA Software Programmer's Guide is intended to provide information for programming the XGA subsystem which is implemented in the IMS G190 XGA serializes palette DAC and the IMS G200 XGA display controller.

This guide contains an overview of the XGA architecture, a description of the XGA subsystem function, and information on programming XGA device registers with programming examples. It should be used in conjunction with the following documents:

This 1st edition of the XGA Software Programmer's Guide (document revision 00) will be superseded by the 2nd edition which is in preparation.

Contents

	Contents overview
	Preface

XGA function

1	XGA Overview
	1.1	Major Components
		1.1.1	System Bus Interface
		1.1.2	Memory and CRT Controller
	1.2	Coprocessor
		1.2.1	Video Memory
	1.3	Attribute Controller
	1.4	Sprite Controller
	1.5	The Serializer, Palette and DAC
	1.6	A/N Font and Sprite Buffer
	1.7	Modes Of Operation
	1.8	Compatibility
		1.8.1	8514/A
		1.8.2	LIM EMS Drivers

2	VGA

3	132 Column Text

4	Extended Graphics
	4.1	Display Controller Description
		4.1.1	Video Memory Format
		4.1.2	Pixel Color Mapping
		4.1.3	Border Color Mapping
		4.1.4	Direct Access to the Video Memory
			System Apertures Into Video Memory
		4.1.5	CRT Controller
			CRTC Register Interpretations
			Scrolling
		4.1.6	Sprite
			Sprite Color Mapping
			Sprite Buffer Accesses
			Sprite Positioning
		4.1.7	Palette
			Palette Accesses
	4.2	Direct Color Mode
			Coprocessor Functions
	4.3	Display Controller Registers
		4.3.1	Register Usage Guidelines
		4.3.2	Direct Access I/O Registers
			Operating Mode Register (Address: 21x0)
			Aperture Control Register (Address: 21x1)
			Interrupt Enable Register (Address: 21x4)
			Interrupt Status Register (Address: 21x5)
			Virtual Memory Control Register (Address: 21x6)
			Virtual Memory Interrupt Status Register (Address: 21x7)
			Aperture Index Register (Address: 21x8)
			Memory Access Mode Register (Address: 21x9)
			Index Register (Address: 21xA)
			Data Registers (Addresses: 21xB to 21xF)
		4.3.3	Indexed Access I/O Registers
			Auto-Configuration Register (Index: 04)
			Coprocessor Save/Restore Data Registers (Index: 0C & 0D)
			Horizontal Total Registers (Index: 10 & 11)
			Horizontal Display End Registers (Index: 12 & 13)
			Horizontal Blanking Start Registers (Index: 14 & 15)
			Horizontal Blanking End Registers (Index: 16 & 17)
			Horizontal Sync Pulse Start Registers (Index: 18 & 19)
			Horizontal Sync Pulse End Registers (Index: 1A & 1B)
			Horizontal Sync Pulse Position Registers (Index: 1C & 1E)
			Vertical Total Registers (Index: 20 & 21)
			Vertical Display End Registers (Index: 22 & 23)
			Vertical Blanking Start Registers (Index: 24 & 25)
			Vertical Blanking End Registers (Index: 26 & 27)
			Vertical Sync Pulse Start Registers (Index: 28 & 29)
			Vertical Sync Pulse End Register (Index: 2A)
			Vertical Line Compare Registers (Index: 2C & 2D)
			Sprite Horizontal Start Registers (Index: 30 & 31)
			Sprite Horizontal Preset (Index: 32)
			Sprite Vertical Start Registers (Index: 33 & 34)
			Sprite Vertical Preset (Index: 35)
			Sprite Control Register (Index: 36)
			Sprite Color Registers (Index: 38 - 3D)
			Display Pixel Map Offset Registers (Index: 40 - 42)
			Display Pixel Map Width Registers (Index: 43 & 44)
			Display Control 1 Register (Index: 50)
			Display Control 2 Register (Index: 51)
			Display ID and Comparator (Index: 52)
			Clock Frequency Select Register (Index: 54)
			Border Color Register (Index: 55)
			Sprite/Palette Index Registers (Index: 60 & 61)
			Sprite/Palette Index Registers with Prefetch (Index: 62 & 63)
			Palette Mask Register (Index: 64)
			Palette Data Register (Index: 65)
			Palette Sequence Register (Bits 2:0 only) (Index: 66)
			Palette Red Prefetch Register (Index: 67)
			Palette Green Prefetch Register (Index: 68)
			Palette Blue Prefetch Register (Index: 69)
			Sprite Data Register (Index: 6A)
			Sprite Prefetch Register (Index: 6B)
			External Clock Select Register (Index: 70)
	4.4	Coprocessor Description
	4.5	Programmer's View
	4.6	Pixel Formats
		4.6.1	Pixel Data
			Fixed And Variable Data
			XGA Function
		4.6.2	The Coprocessor View of Memory
		4.6.3	XGA Pixel Maps
			Pixel Maps A, B, And C (General Maps)
			Pixel Map M (Mask Map)
			Map Origin
			X and Y Pointers
			Scissoring With The Mask Map
		4.6.4	Drawing Operations
			Draw and Step
			Line Draw
			Pixel Block Transfer (PxBlt)
			Area Fill
		4.6.5	Logical And Arithmetic Functions
			Mixes
			Breaking the ALU Carry Chain
			Generating The Pattern From The Source
			Color Expansion
			Pixel Bit Masking
			Color Compare
		4.6.6	Controlling Coprocessor Operations
			Starting a Coprocessor Operation
			Suspending a Coprocessor Operation
			Terminating a Coprocessor Operation
		4.6.7	Coprocessor Operation Completion
			Accesses To The Coprocessor During An Operation
		4.6.8	Coprocessor State Save/Restore
			Suspending Coprocessor Operations
		4.6.9	Save/Restore Mechanism
	4.7	Coprocessor Registers
		4.7.1	Register Usage Guidelines
		4.7.2	Virtual Memory Registers
			Page Directory Base Address Register (Coprocessor Registers, Offset: 0)
			Current Virtual Address Register (Coprocessor Registers, Offset: 4)
		4.7.3	State Save/Restore Registers
			Coprocessor Control Register (Offset: 11)
			State Length Registers (Offset: C & D)
			Save/Restore Data Ports (I/O Index: C & D)
		4.7.4	Pixel Interface Registers
			Pixel Map Index Register (Offset: 12)
			Pixel Map n Base Pointer (Offset: 14)
			Pixel Map n Width (Offset: 18)
			Pixel Map n Height (Offset: 1A)
			Pixel Map n Format (Offset: 1C)
			Pixel Maps A, B and C
			Mask Map
			Bresenham Error Term E (Offset: 20)
			Bresenham Constant K1 (Offset: 24)
			Bresenham Constant K2 (Offset: 28)
			Direction Steps Register (Offset: 2C)
			Foreground Mix Register (Offset: 48)
			Background Mix Register (Offset: 49)
			Destination Color Compare Condition (Offset: 4A)
			Destination Color Compare Value (Offset: 4C)
			Pixel Bit Mask (Plane Mask) (Offset: 50)
			Carry Chain Mask (Offset: 54)
			Foreground Color Register (Offset: 58)
			Background Color Register (Offset: 5C)
			Operation Dimension 1 (Offset: 60)
			Operation Dimension 2 (Offset: 62)
			Mask Map Origin X Offset (Offset: 6C)
			Mask Map Origin Y Offset (Offset: 6E)
			Source X Address (Offset: 70)
			Source Y Address (Offset: 72)
			Pattern X Address (Offset: 74)
			Pattern Y Address (Offset: 76)
			Destination X Address (Offset: 78)
			Destination Y Address (Offset: 7A)
			Pixel Operations Register (Offset: 7C)

5	XGA System Interface
	5.1	Multiple Instances
		5.1.1	Multiple XGA Subsystems in VGA Mode
		5.1.2	Multiple XGA Subsystems in 132 Column Text Mode
		5.1.3	Multiple XGA Subsystems in Extended Graphics Mode
	5.2	XGA POS Registers
		5.2.1	Register Usage Guidelines
		5.2.2	Subsystem Identification Low Byte (Base + 0)
		5.2.3	Subsystem Identification High Byte (Base + 1)
		5.2.4	POS Register 2 (Base + 2)
			XGA Enable (EN, Bit 0)
			I/O Device Address (IODA, Bits 1-3)
			ROM Address (ROM Addr, Bits 4-7)
		5.2.5	POS Register 4 (Base + 4)
			Video Memory Base Address (Bits 7-1)
			Video Memory Enable (VE, Bit 0)
	5.3	POS register 5 (Base + 5)
			1 Mbyte Aperture Base Address (1 Mbyte Base, Bits 3-0)
	5.4	Virtual Memory Description
		5.4.1	Address Translation
			Page Directory and Page Table Entries
		5.4.2	The XGA Implementation of Virtual Memory
			The TLB
			TLB Misses
			System Coherency
			VM Page Not Present Interrupts
			VM Protection Violation Interrupts
			The XGA in Segmented Systems
	5.5	Virtual Memory Registers
		5.5.1	Page Directory Base Address Register (Coprocessor Registers, Offset: 0)
		5.5.2	Current Virtual Address Register (Coprocessor Registers, Offset: 4)
		5.5.3	Virtual Memory Control Register (I/O Address: 21x6)
		5.5.4	Virtual Memory Interrupt Status Register (I/O Address: 21x7)

XGA programming considerations

6	Adapter Co-existence
	6.1	Co-existence with VGA
	6.2	Co-existence with Other XGA Subsystems

7	Locating the XGA Subsystem
	7.1	Reading POS Data
	7.2	Address Calculations
		7.2.1	ROM address
		7.2.2	Coprocessor Registers
		7.2.3	I/O Registers
		7.2.4	The Video Memory Base Address
			4 Mbyte System Video Memory Aperture
			Video Memory Location in Coprocessor Address Space
		7.2.5	1 Mbyte Aperture Base Address
	7.3	Display Type and Video Memory Size

8	VGA Primary Adapter Considerations
	8.1	Chaining the Int 10h Video BIOS Handler
	8.2	Int 24h, Critical Error Handler
	8.3	Int 23h Ctrl-Break Exit Address
	8.4	Int 21h Function 4Ch Program Terminate function

9	General Systems Considerations
	9.1	Co-existing with LIM Expanded Memory Managers
	9.2	Screen Switch Notification, Int 2Fh

10	Extended Graphics Modes Selection
	10.1	Modes Available

11	Mode Setting the XGA Subsystem
	11.1	Individual Mode Setting Procedures
		11.1.1	Extended Graphics Mode
		11.1.2	VGA Mode
		11.1.3	132 Column Text Mode
	11.2	System Video Memory Apertures
		11.2.1	64K System Video Memory Aperture
		11.2.2	1 Mbyte System Video Memory Aperture
		11.2.3	4 Mbyte System Video Memory Aperture
	11.3	Physical Addressability to System Memory
		11.3.1	Real Mode DOS Environments
			Extended Memory
			LIM EMS Managers
		11.3.2	32 bit DOS Extended Environments
		11.3.3	Multiple Virtual DOS Machine Environments
		11.3.4	Protect Mode 16 Bit Segmented Environments
			64K Segment Limit
			Segment Motion
			System Overheads
			Access to XGA Registers and System Memory Apertures
			Suggested Design Model
		11.3.5	Paged Virtual Memory (VM) Environments
			4K Discontiguous Pages
			Page Table Coherency
			System Overheads
			Access to XGA Registers and System Memory Apertures
			Suggested Design Model
		11.3.6	Video Memory Addressability in VM Mode
		11.3.7	System Memory Access Limitation

12	Upwards Compatibility
	12.1	XGA Subsystem POS ID Allocations
	12.2	General Register Usage
	12.3	Video BIOS Mode 14h
	12.4	PS/2 Video Memory Apertures

13	Programming the XGA Subsystem in Extended Graphics Mode
	13.1	XGA Coprocessor Pixel Interface Registers
		13.1.1	Pixel Map Index Register (OFFSET 12h)
		13.1.2	Pixel Map Base Address Register (OFFSET 14h)
		13.1.3	Pixel Map Width Register (OFFSET 18h)
		13.1.4	Pixel Map Height Register (OFFSET 20h)
		13.1.5	Pixel Map Format Register (OFFSET 1Ch)
		13.1.6	Other Registers
	13.2	Using the Coprocessor to Perform a Pixel Blit (PxBlt)
		13.2.1	Mixes and Colors
			Foreground and Background Mix Registers
			Foreground & Background Color Registers
		13.2.2	PxBlt Dimensions
		13.2.3	Pixel Map, Source & Destination
			Source Map X and Y Registers
			Destination Map X and Y Registers
			Pattern Map X and Y Registers
			Mask Map Origin X and Y Offset Registers
		13.2.4	Pixel Operations Register
			Background Source
			Foreground Source
			Step Function
			Source Pixel Map
			Destination Pixel Map
			Pattern Pixel Map
			Mask Pixel Map
			Drawing Mode
			Direction Octant
			Conclusion
	13.3	Using the Coprocessor to Perform a Bresenham Line Draw
		13.3.1	Mixes and Colors
			Foreground and Background Mix Registers
			Foreground and Background Color Registers
		13.3.2	Bresenham Line Draw
			Bresenham Error Term Register
			Bresenham Constant K1 Register
			Bresenham Constant K2 Register
			Operation Dimension Registers
		13.3.3	Pixel Map, Source and Destination
			Source Map X and Y Registers
			Destination Map X and Y Registers
			Pattern Map X and Y Registers
			Mask Map Origin X and Y Offset Registers
		13.3.4	Pixel Operations Register
			Background Source
			Foreground Source
			Step Function
			Source Pixel Map
			Destination Pixel Map
			Pattern Pixel Map
			Mask Pixel Map
			Drawing Mode
			Direction Octant
			Conclusion
	13.4	Memory Access Modes (Reg. 21x9)
	13.5	Motorola/Intel Format
		13.5.1	System Processor Access
		13.5.2	XGA Coprocessor Accesses
		13.5.3	Exploitation

14	Other Programming Considerations
	14.1	Overlapping BitBlits
		14.1.1	Pixel Block Transfer (PxBlt)
		14.1.2	Inverting PxBlt
	14.2	Sprite Handling
		14.2.1	Sprite Loading
		14.2.2	Sprite Positioning
	14.3	Waiting for Hardware Not Busy
	14.4	Destination Bitmap Width Restriction
	14.5	Line Length Restriction
	14.6	System Register Usage
	14.7	Direct Color Mode
		14.7.1	Palette Loading
		14.7.2	Coprocessor Support

15	Sample Code
	15.1	Putting the XGA Subsystem into Extended Graphics Mode
		15.1.1	Pseudo Code
		15.1.2	Code Example
			Main C Program
			Assembler Subroutines
	15.2	Putting the XGA Subsystem into 132 Column Text Mode
		15.2.1	Pseudo Code
		15.2.2	Code Example
			Main C Program
			Assembler Subroutines

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